Table of Contents
Advertisement
Quick Links
Advertisement
Table of Contents
Subscribe to Our Youtube Channel
Related Manuals for GOWIN DK START GW1N-LV9LQ144C6I5 V2.1
Summary of Contents for GOWIN DK START GW1N-LV9LQ144C6I5 V2.1
- Page 1 DK_START_GW1N-LV9LQ144C6I5_V2.1 User Guide DBUG399-1.0E, 08/17/2021...
- Page 2 Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
- Page 3 Revision History Date Version Description 08/17/2021 1.0E Initial version published.
-
Page 4: Table Of Contents
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 2 1.4 Support and Feedback ....................... 3 2 Introduction ...................... - Page 5 3.8 GPIO ..........................16 3.8.1 Overview ........................16 3.8.2 GPIO Circuit ........................16 3.8.3 Pinout ..........................17 3.9 MIPI/LVDS ........................19 3.9.1 Overview ........................19 3.9.2 MIPI/LVDS Circuit ......................19 3.9.3 Pinout ..........................20 4 Consideration ....................23 5 Gowin Software....................24 DBUG399-1.0E...
-
Page 6: List Of Figures
List of Figures List of Figures Figure 2-1 DK_START_GW1N-LV9LQ144C6I5_V2.1 Development Board ........4 Figure 2-2 A Development Kit ......................5 Figure 2-3 PCB Components ......................6 Figure 2-4 System Block Diagram ..................... 6 Figure 3-1 FPGA USB Download Diagram ..................11 Figure 3-2 Power System Distribution .................... - Page 7 List of Tables List of Tables Table 1-1 Terminology and Abbreviations ..................2 Table 2-1 Development Board Description ..................8 Table 3-1 FPGA Download Pinout ..................... 11 Table 3-2 FPGA Power Pinout ......................12 Table 3-3 FPGA Clock Pinout ......................13 Table 3-4 LED Pinout .........................
-
Page 8: About This Guide
1. DS100, GW1N series of FPGA Products Data Sheet 2. UG103, GW1N series of FPGA Products Package and Pinout Manual 3. UG801, GW1N-9 Pinout 4. UG290, Gowin FPGA Products Programming and Configuration Guide 5. SUG100, Gowin Software User Guide DBUG399-1.0E... -
Page 9: Terminology And Abbreviations
1 About This Guide 1.3 Terminology and Abbreviations 1.3 Terminology and Abbreviations The terminology and abbreviations used in this manual are as shown in Table 1-1. Table 1-1 Terminology and Abbreviations Terminology and Abbreviations Meaning FPGA Field Programmable Gate Array System in Package SDRAM Synchronous Dynamic RAM... -
Page 10: Support And Feedback
1 About This Guide 1.4 Support and Feedback 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com... -
Page 11: Introduction
2.1 Overview Figure 2-1 DK_START_GW1N-LV9LQ144C6I5_V2.1 Development Board The development board uses Gowin GW1N-9 FPGA devices. The GW1N series of FPGA products are the first generation of the Gowin ® LittleBee family and it is an SIP chip. It has the characteristics of low power consumption, instant-start, low cost, non-volatility, high security, rich packages, convenient and flexible usage, etc., which can effectively reduce... -
Page 12: Development Kit
2 Introduction 2.2 Development Kit 2.2 Development Kit A development board suite includes the following items: DK_START_GW1N-LV9LQ144C6I5_V2.1 development board USB Cable Figure 2-2 A Development Kit ① DK_START_GW1N-LV9LQ144C6I5_V2.1 development board ② USB Cable DBUG399-1.0E 5(24) -
Page 13: Pcb Components
2 Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components 2.5V 1.2V 3.3V LVDS/MIPI FPGA Download 5V IN Switch FPGA GPIO GPIO LVDS/MIPI LVDS/MIPI 2.4 System Block Diagram Figure 2-4 System Block Diagram 2*BUTTON 2*SWITCH 4*LED 50MHz 5Pairs 10Pairs LVDS/MIPI LVDS/MIPI... -
Page 14: Features
2 Introduction 2.5 Features 2.5 Features The structure and features of the development board are as follows: 1. FPGA LQFP144 package Up to 120 user I/O Embedded flash, data not easily lost if power down Abundant LUT4 resources ... -
Page 15: Development Board Description
2 Introduction 2.6 Development Board Description 2.6 Development Board Description Table 2-1 Development Board Description Name Functional Description Technical Condition Note FPGA Core chip – – Support an USB USB to JTAG chip integrated interface; Support Download – on board JTAG, AUTOBOOT ... - Page 16 2 Introduction 2.6 Development Board Description Name Functional Description Technical Condition Note Humidity – – Temperature – Operating range: –20°~70° – DBUG399-1.0E 9(24)
-
Page 17: Development Board Circuit
3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module Overview For the resources of GW1N series of FPGA Products, see DS100, GW1N Series of FPGA Products Data Sheet. I/O BANK Introduction For the I/O BANK, package, and pinout information, see UG103, GW1N Series of FPGA Products Package and Pinout User Guide. -
Page 18: Usb Download Circuit
3 Development Board Circuit 3.3 Power Supply 3.2.2 USB Download Circuit Figure 3-1 FPGA USB Download Diagram 3.2.3 Download Flow Please plug USB download cable into the USB interface (J6) of the development board to download FPGA, and then open Programmer, click SRAM mode or Embedded flash mode to download bit stream file to SRAM or flash. -
Page 19: Power System Distribution
3 Development Board Circuit 3.3 Power Supply 3.3.2 Power System Distribution Figure 3-2 Power System Distribution Interface DC 5V Input USB-to-JTAG （FT2232） TPS7A7001 Key & LED& Reset 3.3V & Switch & VCCO3 FPGA VCCO2 (LVDS) TPS7A7001 FPGA VCCX & 2.5V VCCO0 &... -
Page 20: Clock
3 Development Board Circuit 3.4 Clock 3.4 Clock 3.4.1 Overview The development board provides a 50MHz crystal oscillator connected to the PLL input pin. This can be employed as the input clock for the PLL in FPGA. Frequency division and multiplication of PLL can provide clocks required by users. -
Page 21: Led Circuit
3 Development Board Circuit 3.6 Switches 3.5.2 LED Circuit Figure 3-4 LED Circuit 3.5.3 Pinout Table 3-4 LED Pinout Name Pin No. BANK Description I/O Level F_LED1 LED1 2.5V/1.2V F_LED2 LED2 2.5V/1.2V F_LED3 LED3 2.5V/1.2V F_LED4 LED 4 2.5V/1.2V 3.6 Switches 3.6.1 Overview Two Slide switches are incorporated into the development board. -
Page 22: Pinout
3 Development Board Circuit 3.7 Key 3.6.3 Pinout Table 3-5 Switch Circuit Pinout Name Pin No. BANK Description I/O Level F_SW1 Slide Switch1 2.5V/1.2V F_SW2 Slide Switch2 2.5V/1.2V 3.7 Key 3.7.1 Overview Two key switches are embedded in the development board. Users can manually input a low level to the corresponding FPGA pins for testing purposes. -
Page 23: Gpio
3 Development Board Circuit 3.8 GPIO 3.8 GPIO 3.8.1 Overview One 2.54mm DC3-20P socket and one 2.54mm DC3-40P socket are reserved in the development board to facilitate the users to do the function expansion and testing. 3.8.2 GPIO Circuit Figure 3-7 GPIO Circuit H_B_IO1 H_B_IO2 H_B_IO4... -
Page 24: Pinout
3 Development Board Circuit 3.8 GPIO 3.8.3 Pinout Table 3-7 J14 GPIO Pinout Name Pin No. Socket Pin No. BANK Description I/O Level H_A_IO1 General I/O 3.3V H_A_IO2 General I/O 3.3V H_A_IO3 General I/O 3.3V H_A_IO4 General I/O 3.3V H_A_IO5 General I/O 3.3V H_A_IO6... - Page 25 3 Development Board Circuit 3.8 GPIO Name Pin No. Socket Pin No. BANK Description I/O Level H_B_IO11 General I/O 2.5V/1.2V H_B_IO12 General I/O 2.5V/1.2V H_B_IO13 General I/O 2.5V/1.2V H_B_IO14 General I/O 2.5V/1.2V H_B_IO15 General I/O 2.5V/1.2V H_B_IO16 General I/O 2.5V/1.2V H_B_IO17 General I/O 2.5V/1.2V...
-
Page 26: Mipi/Lvds
3 Development Board Circuit 3.9 MIPI/LVDS 3.9 MIPI/LVDS 3.9.1 Overview Two 2-mm DC3-20P sockets are reserved in the development board for MIPI/LVDS input/output performance testing and high-speed data transmission. Up to 10 pairs of differential input and 10 pairs of differential output can be satisfied. -
Page 27: Pinout
3 Development Board Circuit 3.9 MIPI/LVDS 3.9.3 Pinout Table 3-9 J15 FPGA Pinout (IDES 16: 1 Supported) FPGA Socket Name BANK Description I/O Level Pin No. Pin No. 2.5V(LVDS)/ Differential input F_LVDS_A1_P channel 1+ 1.2V(MIPI) 2.5V(LVDS)/ Differential input F_LVDS_A1_N channel 1- 1.2V(MIPI) 2.5V(LVDS)/ Differential input... -
Page 28: Table 3-10 J16 Fpga Pinout (Ides 16: 1 Supported)
3 Development Board Circuit 3.9 MIPI/LVDS Table 3-10 J16 FPGA Pinout (IDES 16: 1 Supported) FPGA Socket Name BANK Description I/O Level Pin No. Pin No. 2.5V(LVDS)/ Differential output F_LVDS_B1_P channel 1+ 1.2V(MIPI) 2.5V(LVDS)/ Differential output F_LVDS_B1_N channel 1- 1.2V(MIPI) 2.5V(LVDS)/ Differential output F_LVDS_B2_P... -
Page 29: Table 3-11 J18 Fpga Pinout (Ides 16: 1 Supported)
3 Development Board Circuit 3.9 MIPI/LVDS Table 3-11 J18 FPGA Pinout (IDES 16: 1 Supported) FPGA Socket Name BANK Description I/O Level Pin No. Pin No. 2.5V(LVDS)/ Differential output F_LVDS_B6_P channel 6+ 1.2V(MIPI) 2.5V(LVDS)/ Differential output F_LVDS_B6_N channel 6- 1.2V(MIPI) 2.5V(LVDS)/ Differential output F_LVDS_B7_P... -
Page 30: Consideration
4 Consideration Consideration Considerations for the use of development board 1. Handle with care and pay attention to electrostatic protection; 2. VCCO2 Bank voltage needs to be set as 2.5V when the Bank2 output differential pairs serve as LVDS output; VCCO2 Bank voltage needs to be set as 1.2V when the Bank2 output differential pairs serve as MIPI output. -
Page 31: Gowin Software
5 Gowin Software Gowin Software See SUG100, Gowin Software User Guide for details. DBUG399-1.0E 24(24)
Need help?
Do you have a question about the DK START GW1N-LV9LQ144C6I5 V2.1 and is the answer not in the manual?
Questions and answers