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Related Manuals for GOWIN DK Motor GW2A-LV55PG484C8I7 V3.0
Summary of Contents for GOWIN DK Motor GW2A-LV55PG484C8I7 V3.0
- Page 1 DK_Motor_GW2A-LV55PG484C8I7_V3.0 User Guide DBUG410-1.0.1E, 03/17/2023...
- Page 2 Copyright © 2023 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. is the trademark of Guangdong Gowin Semiconductor Corporation and is registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
- Page 3 Revision History Date Version Description 06/28/2022 1.0E Initial version published. Chapter 4 “Quick Start” removed. “Figure 2-4 System Block Diagram” in Chapter 2 “Development 03/17/2023 1.0.1E Board Introduction” updated. “Table 3-3 Ethernet Interface Pinout” in Chapter 3.5.2 "Pinout” updated.
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Page 4: Table Of Contents
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 2 1.4 Support and Feedback ....................... 2 2 Development Board Introduction .............. -
Page 5: Contents
Contents 3.5.1 Introduction ........................11 3.5.2 Pinout ..........................11 3.6 FSMC interface ......................... 13 3.6.1 Introduction ........................13 3.6.2 Pinout ..........................13 3.7 ELVDS interface ....................... 15 3.7.1 Introduction ........................15 3.7.2 Pinout ..........................15 3.8 Motor Control Interface ..................... 16 3.8.1 Introduction ........................ -
Page 6: List Of Figures
List of Figures List of Figures Figure 2-1 DK_Motor_GW2A-LV55PG484C8I7_V3.0 Development Board ........3 Figure 2-2 A Development Board Suite ..................... 4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Block Diagram ..................... 5 Figure 3-1 FPGA Download and Configuration Connection Diagram ..........9 Figure 3-2 Clock and Reset Connection Diagram ................ - Page 7 List of Tables List of Tables Table 1-1 Abbreviations and Terminology ..................2 Table 3-1 FPGA Download and Configuration Pinout ................ 9 Table 3-2 Clock and Reset Pinout...................... 10 Table 3-3 Ethernet Interface Pinout ....................11 Table 3-4 FSMC Interface Pinout ....................... 13 Table 3-5 ELVDS Interface Pinout .....................
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Page 8: About This Guide
DS102, GW2A series of FPGA Products Data Sheet UG113, GW2A-55 Pinout UG111, GW2A series of FPGA Products Package and Pinout User Guide UG290, GW1N series of FPGA Products Programming and Configuration User Guide SUG100, Gowin Software User Guide DBUG410-1.0.1E 1(21) -
Page 9: Terminology And Abbreviations
Low-voltage Differential Signaling SSRAM Shadow Static Random Access Memory 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com... -
Page 10: Development Board Introduction
Figure 2-1 DK_Motor_GW2A-LV55PG484C8I7_V3.0 Development Board The development board uses the GW2A- LV55PG484 FPGA device, which is the first generation product of Gowin Arora family. The GW2A series of FPGA products offer abundant resources like high-performance DSP, high-speed LVDS interface and BSRAM. These embedded resources... -
Page 11: A Development Board Kit
2 Development Board Introduction 2.2 A Development Board Kit motor communication, and GPIO interface. External FLASH chip is used to store FPGA configuration programs; There are keys and LEDs that you can use to debug. 2.2 A Development Board Kit The development board kit includes the following items: 1. -
Page 12: Pcb Components
2 Development Board Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components 1.2V Power Switch 3.3V 5V IN Ethernet RS422 Interface Ethernet Motor PHY Chip Interface Ethernet RS485 Interface Ethernet PHY Chip RS422 Motor Ethernet Interface Ethernet Interface PHY Chip RS485 ELVDS... -
Page 13: Features
2 Development Board Introduction 2.5 Features 2.5 Features The key features are as follows: 1. The FPGA device Gowin GW2A-LV55PG484 FPGA 319 Max. user I/O 2. Download and Boot Integrate download module on the board, download through Mini B ... - Page 14 2 Development Board Introduction 2.5 Features Two 24 PIN double-row pins, each including 19 GPIOs. I/O Bank voltage is 3.3V, leading to three ground pins. 13. Debug module Four keys Four green LEDs DBUG410-1.0.1E 7(21)
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Page 15: Development Board Circuit
3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module Overview For the resources of GW2A-LV55PG484 FPGA products, please refer DS102, GW2A Series of FPGA Products. I/O BANK Introduction For the I/O BANK, package, and pinout information, see UG111, GW2A Series of FPGA Products Package and Pinout User Guide for more... -
Page 16: Pinout
3 Development Board Circuit 3.3 Power Supply Figure 3-1 FPGA Download and Configuration Connection Diagram 3.2.2 Pinout Table 3-1 FPGA Download and Configuration Pinout Signal Name FPGA Pin No. BANK I/O Level Description JTAG_TCK 3.3V JTAG Signal JTAG_TDO 3.3V JTAG Signal JTAG_TDI 3.3V JTAG Signal... -
Page 17: Clock And Reset
3 Development Board Circuit 3.4 Clock and Reset Adopt one FP6165ADXR-G1 DC-DC power supply chip to generate 1.0V, and the maximum output current is 3A. 3.4 Clock and Reset 3.4.1 Introduction The development board offers a 25MHz oscillator connecting to the global clock pins. -
Page 18: Ethernet
3 Development Board Circuit 3.5 Ethernet 3.5 Ethernet 3.5.1 Introduction The development board is equipped with three KSZ8081MNXCA-TR chips, supporting MII interface. Figure 3-3 FPGA and Ethernet Interface Connection Diagram TXD[3:0] RXD[3:0] CRS,COL RXER,RXC,RXDV TXER,TXC CLK,RST_N KSZ8081MNXCA TXD[3:0] RXD[3:0] CRS,COL RXER,RXC,RXDV TXER,TXC CLK,RST_N... - Page 19 3 Development Board Circuit 3.5 Ethernet Signal Name FPGA Pin No. BANK I/O Level Description MII receiving data PHY1_RXD0 3.3V MII receiving data PHY1_RXD1 3.3V MII receiving data PHY1_RXD2 3.3V MII receiving data PHY1_RXD3 3.3V MII clock input PHY_MDC 3.3V MII data input/output PHY_MDIO 3.3V...
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Page 20: Fsmc Interface
3 Development Board Circuit 3.6 FSMC interface Signal Name FPGA Pin No. BANK I/O Level Description PHY3_RXDV MII receiving data, valid 3.3V MII receiving data PHY2_RXD0 3.3V MII receiving data PHY2_RXD1 3.3V MII receiving data PHY2_RXD2 3.3V MII receiving data PHY2_RXD3 3.3V Clock input... - Page 21 3 Development Board Circuit 3.6 FSMC interface Signal Name FPGA Pin No. BANK I/O Level Description FSMC_D6 3.3V Data FSMC_D7 3.3V Data FSMC_D8 3.3V Data FSMC_D9 3.3V Data FSMC_D10 3.3V Data FSMC_D11 3.3V Data FSMC_D12 3.3V Data FSMC_D13 3.3V Data FSMC_D14 3.3V Data...
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Page 22: Elvds Interface
3 Development Board Circuit 3.7 ELVDS interface 3.7 ELVDS interface 3.7.1 Introduction ELVDS interface are 12 SMA sockets, including 6 pairs of differential signals. These interfaces are also used as GPIOs. The connection diagram is as follows: Figure 3-5 ELVDS Interface Diagram 3.7.2 Pinout Table 3-5 ELVDS Interface Pinout Signal Name... -
Page 23: Motor Control Interface
3 Development Board Circuit 3.8 Motor Control Interface 3.8 Motor Control Interface 3.8.1 Introduction There are two motor control interfaces on the development board for the communication between FPGA and motor. The connection diagram is as follows: Figure 3-6 Connection Diagram of Motor Control Interface RS422_OUT1_A RS422_OUT1_B RS422... - Page 24 3 Development Board Circuit 3.8 Motor Control Interface Signal Name FPGA Pin No. BANK I/O Level Description RS485 Transceiver Receiving RS485_DATA1_RX V6 3.3V Signal RS485 Transceiver Signal RS485_DATA1_CT 3.3V Direction Control RS485 Transceiver RS485_CLK1_TX 3.3V Transmitting Signal RS485 Transceiver Receiving RS485_CLK1_RX 3.3V Signal...
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Page 25: Pwm Interface
3 Development Board Circuit 3.9 PWM interface 3.9 PWM interface 3.9.1 Introduction There are two PWM interfaces on the development board. These pins can also be used as GPIOs. The connection diagram is as follows: Figure 3-7 PWM Interface Connection Diagram ADC_DIN2 ADC_DIN1 ADC_SCLK1... - Page 26 3 Development Board Circuit 3.9 PWM interface Signal Name FPGA Pin No. BANK I/O Level Description Phase V PWM upper V_PWM_BOTTOM_N1 3.3V leg control signal SC_RESET_N1 3.3V Reserved IO SC_N1 3.3V Reserved IO BLEEDER_ON1 3.3V Reserved IO BUS_EN1 3.3V Reserved IO IBUS1 3.3V Reserved IO...
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Page 27: Gpio
3 Development Board Circuit 3.10 GPIO 3.10 GPIO 3.10.1 Introduction There are one 40 PIN double-row pin and two 24 PIN double-row pins. These pins are used as IOs to facilitate user testing. Among them: There are 40 PIN double-row pins, including 36 GPIOs. I/O Bank voltage is 3.3V, leading to two 3.3V voltage and two ground pins. -
Page 28: Key Module
3 Development Board Circuit 3.12 Key Module 3.12 Key Module 3.12.1 Introduction The development board has four keys that can be used to control input during testing. When the key is pressed, the input is low. The connection diagram is shown in Figure 3-9. Figure 3-9 Key Circuit 3.12.2 Pinout Table 3-9 Key Module Pinout...
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