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Related Manuals for GOWIN DK_START_GW1NSR-LX2CQN48PC5I4_V 2.1
Summary of Contents for GOWIN DK_START_GW1NSR-LX2CQN48PC5I4_V 2.1
- Page 1 DK_START_GW1NSR-LX2CQN48PC5I4_V User Guide DBUG401-1.0E, 08/19/2021...
- Page 2 Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
- Page 3 Revision History Date Version Description 08/19/2021 1.0E Initial version published.
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Page 4: Table Of Contents
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Abbreviations and Terminology ................... 1 1.4 Support and Feedback ....................... 3 2 Development Board Description .............. - Page 5 3.8.2 MIPI/LVDS Circuit ......................16 3.8.3 Pinout ..........................17 3.9 ADC........................... 18 3.9.1 Overview ........................18 3.9.2 ADC Circuit ........................19 3.9.3 Pinout ..........................19 4 Considerations .................... 20 5 Gowin Software ................... 21 6 Quick Start ....................22 DBUG401-1.0E...
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Page 6: List Of Figures
List of Figures List of Figures Figure 2-1 DK_START_GW1NSR-LX2CQN48PC5I4_V2.1 Development Board ......4 Figure 2-2 A Development Board Suite ..................... 5 Figure 2-3 PCB Components ......................6 Figure 2-4 System Architecture ......................6 Figure 3-1 Connection Diagram for FPGA USB Downloading ............11 Figure 3-2 Power System Distribution .................... - Page 7 List of Tables List of Tables Table 1-1 Abbreviations and Terminology ..................2 Table 2-1 Development Board Specification ..................8 Table 3-1 FPGA Download and Pinout ....................11 Table 3-2 FPGA Power Pinout ......................13 Table 3-3 FPGA Clock and Reset Pinout ................... 13 Table 3-4 LED Pinout .........................
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Page 8: About This Guide
1. DS861, GW1NSR series of FPGA Products Data Sheet 2. UG863, GW1NSR series of FPGA Products Package and Pinout 3. UG862, GW1NSR-2&2C Pinout 4. UG290, Gowin FPGA Products Programming and Configuration User Guide 5. SUG100, Gowin Software User Guide 1.3 Abbreviations and Terminology The abbreviations and terminology used in this manual are as shown in Table 1-1 below. -
Page 9: Table 1-1 Abbreviations And Terminology
1 About This Guide 1.3 Abbreviations and Terminology Table 1-1 Abbreviations and Terminology Abbreviations and Terminology Full Name FPGA Field Programmable Gate Array System On Chip Advanced RISC Machines Advanced High performance Bus Advanced Peripheral Bus Timer Timer RS232 Universal Asynchronous Receiver/Transmitter NVIC Nested Vector Interrupt Controller Debug Access Port... -
Page 10: Support And Feedback
Delay-locked Loop LQ144 LQFP144 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail: support@gowinsemi.com DBUG401-1.0E... -
Page 11: Development Board Description
2 Development Board Description 2.1 Overview Development Board Description 2.1 Overview Figure 2-1 DK_START_GW1NSR-LX2CQN48PC5I4_V2.1 Development Board The development board adopts the GW1NSR-2 SoC FPGA. SoC FPGA is embedded with an ARM Cortex-M3 hard core processor, 32Mbit PSRAM, 1Mbit User Flash and eight-channel ADC converter, etc. When the ARM Cortex-M3 hard-core processor is employed as the core, the needs of the Min. -
Page 12: A Development Board Suite
2 Development Board Description 2.2 A Development Board Suite 2.2 A Development Board Suite A development board suite includes the following items: DK_START_GW1NSR-LX2CQN48PC5I4_V2.1 development board USB cable Figure 2-2 A Development Board Suite ① DK_START_GW1NSR-LX2CQN48PC5I4_V2.1 development board ② USB Cable DBUG401-1.0E 5(22) -
Page 13: Pcb Components
2 Development Board Description 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components Select FPGA /ARM 2.5V 1.2V 1.8V Download LVDS 3.3V FPGA Download 5V IN FPGA GPIO GPIO Reset LVDS 2.4 System Architecture Figure 2-4 System Architecture 2*LED (Share I/Os 2*BUTTON 50MHz... -
Page 14: Features
2 Development Board Description 2.5 Features 2.5 Features The structure and features of the development board are as follows: 1. FPGA Adopts QN48 package Up to 38 user I/O Embedded flash, data not easily lost if power down ... -
Page 15: Development Board Specification
2 Development Board Description 2.6 Development Board Specification 2.6 Development Board Specification Table 2-1 Development Board Specification Item Functions Technical Conditions Note – – FPGA Core chip Support an USB USB-JTAG module on – Download interface; Support board JTAG, AUTOBOOT ... - Page 16 2 Development Board Description 2.6 Development Board Specification Item Functions Technical Conditions Note MIPI/LVDS, used for 5 pairs of input, 4 pairs of – MIPI/LVDS testing output USB interface ESD protection: ±15kV non-contact discharge, ± 8kV contact discharge; USB interface: ESD ...
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Page 17: Development Board Circuit
3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module Overview For the resources of GW1NSR series of FPGA products, please refer to DS861, GW1NSR series of FPGA Products Data Sheet. I/O BANK Introduction For the I/O BANK, package and pinout information of the GW1NSR series of FPGA products, please refer to UG863, GW1NSR series of FPGA Products Package and Pinout. -
Page 18: Usb Download Circuit
3 Development Board Circuit 3.3 Power Supply 3.2.2 USB Download Circuit Figure 3-1 Connection Diagram for FPGA USB Downloading USB_D+ USB_D- USB-to-JTAG Chip GW1NSR- LX2CQN48PC5I4_V2.1 3.2.3 Download Flow 1. FPGA and MCU download mode: Plug the USB cable to the USB interface (J6) on the development board. -
Page 19: Power System Distribution
3 Development Board Circuit 3.3 Power Supply 3.3.2 Power System Distribution Figure 3-2 Power System Distribution USB Interface DC5V Input USB-JTAG （FT2232） Key&LED&Reset TPS7A7001 3.3V FPGA VCCO0&VCCO3 (ADC/LVDS/MIPI) FPGA VCCX （UX FPGA） FPGA VCCO2 (LVDS) TPS7A7001 2.5V FPGA VCCO1 FPGA VCCO0&VCCO3 TPS7A7001 (PSRAM) -
Page 20: Pinout
3 Development Board Circuit 3.4 Clock, Reset 3.3.1 Pinout Table 3-2 FPGA Power Pinout Signal Name Pin No. BANK Description VCCO0 I/O Bank Power 1.8V/3.3V VCCO1 I/O Bank Power 2.5V VCCO2 I/O Bank Power 1.2V/2.5V VCCO3 I/O Bank Power 1.8V/3.3V VCCX 8, 36 Auxiliary voltage... -
Page 21: Led
3 Development Board Circuit 3.5 LED 3.5 LED 3.5.1 Overview Two green LEDs (share I/O pins with keys) are incorporated into the development board and are used to display the required status. In addition, two LEDs are reserved to signify power supply and FPGA loading status. Users can test the LEDs in the following ways: If the output signal of related pins is logic low, LED is on;... -
Page 22: Key Circuit
3 Development Board Circuit 3.7 GPIO 3.6.2 Key Circuit Figure 3-5 Key Circuit Diagram GW1NSR- LX2CQN48PC5I4_V2.1 3.6.3 Pinout Table 3-5 Key Pinout Signal Name Pin No. BANK Description 1.2V/2.5V F_KEY1 KEY1 3.7 GPIO 3.7.1 Overview One 2.54mm DC3-10P sockets are reserved on the development board for user function extension and testing purposes. -
Page 23: Pinout
3 Development Board Circuit 3.8 MIPI/LVDS 3.7.3 Pinout Table 3-6 J14 GPIO Pinout Signal Name Pin No. Socket Pin No. BANK Description H_A_IO1 General I/O 2.5V H_A_IO2 General I/O 2.5V H_A_IO3 General I/O 2.5V H_A_IO4 General I/O 2.5V H_A_IO5 General I/O 2.5V H_A_IO6 General I/O... -
Page 24: Pinout
3 Development Board Circuit 3.8 MIPI/LVDS 3.8.3 Pinout Table 3-7 J15 FPGA Pinout Socket Signal Name Pin No. BANK Description Pin No. Differential output 2.5V(LVDS)/ F_LVDS_A1_P channel 1+ 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_A1_N channel 1- 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_A2_P channel 2+ 1.2V(MIPI) Differential output... -
Page 25: Adc
3 Development Board Circuit 3.9 ADC Socket Signal Name Pin No. BANK Description Pin No. channel 1- Differential input 3.3V(LVDS)/ F_LVDS_B2_P channel 2+ 1.8V(MIPI) Differential input 3.3V(LVDS)/ F_LVDS_B2_N channel 2- 1.8V(MIPI) Differential input 3.3V(LVDS)/ F_LVDS_B3_P channel 3+ 1.8V(MIPI) Differential input 3.3V(LVDS)/ F_LVDS_B3_N channel 3-... -
Page 26: Adc Circuit
3 Development Board Circuit 3.9 ADC 3.9.2 ADC Circuit Figure 3-8 ADC Circuit F_LVDS_B1_P F_LVDS_B1_N F_LVDS_B2_P F_LVDS_B2_N F_LVDS_B3_P F_LVDS_B3_N F_LVDS_B4_P F_LVDS_B4_N F_LVDS_B5_P F_LVDS_B5_N 3.9.3 Pinout Table 3-9 J15 ADC Pinout Signal Name Pin No. Socket Pin No. BANK Description ADC_CH0 ADC_CH0 3.3V(ADC) ADC_CH1... -
Page 27: Considerations
4 Considerations Considerations Considerations for the use of the development board: 1. Handle with care and pay attention to electrostatic protection; 2. Programs download: Before downloading to FPGA and MCU, switch the SW3, SW4, SW5, and SW6 on the development board to the FPGA Download side;... -
Page 28: Gowin Software
5 Gowin Software Gowin Software Please refer to SUG100, Gowin Software User Guide for details. DBUG401-1.0E 21(22) -
Page 29: Quick Start
6 Quick Start Quick Start See TN432, DK-START-GW1NSR2_V2.1 Development Board Quick Start User Guide for details. DBUG401-1.0E 22(22)
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