Espressif Systems ESP32-C3 Series Hardware Design Manuallines page 13

2 Schematic Checklist
Software can read the values of GPIO2, GPIO8 and GPIO10 from GPIO_STRAPPING field in GPIO_STRAP_REG
register. For register description, please refer to Section GPIO Matrix Register Summary in
ESP32-C3 Technical Reference
During the chip's system reset, the latches of the strapping pins sample the voltage level as strapping bits of "0"
or "1", and hold these bits until the chip is powered down or shut down.
Types of system reset include:
• power-on-reset
• RTC watchdog reset
• brownout reset
• analog super watchdog reset
• crystal clock glitch detection reset
By default, GPIO9 is connected to the internal pull-up resistors. If GPIO9 is not connected or connected to an
external high-impedance circuit, the internal weak pull-up/pull-down will determine its default input level.
To change the strapping bit values, you can apply the external pull-down/pull-up resistances, or use the host
MCU's GPIOs to control the voltage level of these pins when powering on ESP32-C3 family.
After reset, the strapping pins work as normal-function pins.
Refer to Table 2 for a detailed boot-mode configuration of the strapping pins.
Pin Default
GPIO2 N/A
GPIO8 N/A
GPIO9 Pull-up
Pin Default
GPIO8 N/A
Pin Default
GPIO10 N/A
1
The strapping combination of GPIO8 = 0 and GPIO9 = 0 is invalid and will trigger unexpected
behavior.
Figure 10 shows the setup and hold times for the strapping pin before and after the CHIP_PU signal goes high.
Espressif Systems
Manual.
Table 2: Strapping Pins
Booting Mode
SPI Boot
1
Don't care
1
Enabling/Disabling ROM Code Print During Booting
Functionality
When the value of eFuse field EFUSE_UART_PRINT_CONTROL is
0 (default), print is enabled and not controlled by GPIO8.
1, if GPIO8 is 0, print is enabled; if GPIO8 is 1, it is disabled.
2, if GPIO8 is 0, print is disabled; if GPIO8 is 1, it is enabled.
3, print is disabled and not controlled by GPIO8.
Controlling JTAG Signal Source During Booting
Functionality
When the value of eFuse bit EFUSE_STRAP_JTAG_SEL is
0 (default), JTAG signals come from USB Serial/JTAG controller.
1, if GPIO10 is 0, JTAG signals come from chip pins;
if GPIO10 is 1, JTAG signals come from USB Serial/JTAG controller.
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ESP32-C3 Family Hardware Design Guidelines V0.5