Power Supply - Espressif Systems ESP32-C3 Series Hardware Design Manuallines

3 PCB Layout Design

3.3 Power Supply

Figure 15: ESP32­C3 Family Power Traces in a Four­layer PCB Design
• Four-layer PCB design is recommended over two-layer design. Route the power traces on the fourth
(bottom) layer whenever possible. Vias are required for the power traces to go through the layers and get
connected to the pins on the top layer. There should be at least two vias if the main power traces need to
cross layers. The drill diameter on other power traces should be no smaller than the width of the power
traces.
• The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure 15. The width of the main
power traces should be at least 20 mil. The width of the power traces for pin 2 and pin 3 should be at least
15 mil. The width of other power traces is preferably 10 mil.
• As shown in Figure 16, we recommend connecting the capacitor to ground in the LC filter circuit near pin 2
and pin 3 (analog power supply pins) to the third and fourth layer through a via, and maintaining a keep-out
area on other layers.
Figure 16: ESP32­C3 Family Stub in a Four­layer PCB Design
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ESP32-C3 Family Hardware Design Guidelines V0.5