Clock Source; External Clock Source (Compulsory) - Espressif Systems ESP32-C3 Series Hardware Design Manuallines

2 Schematic Checklist
SPIQ
SPID
SPICLK
SPICS0
SPIWP
SPIHD
VDD_SPI
VDD3P3_CPU
GND
ESP32-C3
GND
U1
C1
TBD

2.4 Clock Source

There are two clock sources for ESP32-C3 family, namely an external crystal clock source and an RTC clock
source.
GND
40MHz(±10ppm)

2.4.1 External Clock Source (compulsory)

Currently, the ESP32-C3 family firmware only supports 40 MHz crystal. The specific capacitance of C1 and C2
depends on further testing of, and adjustment to, the overall performance of the whole circuit. We recommend
reserving a series resistor (initially of 0 Ω) on the XTAL_P clock trace to reduce the drive capability of the crystal,
TBD
3 L3
as well as to minimize the impact of crystal harmonics on RF performance. Note that the accuracy of the
2
selected crystal needs to be ±10 ppm.
GND
SPICLK
SPICS0
VDD_SPI
VDD3P3_CPU
ESP32-C3
Y1
3
L3
OUT
2
GND
Espressif Systems
GND
24 R3 0
23
R4 0
22 R5 0
21
20 R6 0
19 R7 0
18
17
C10 C11
0.1uF 1uF
3
GND GND
GND
Figure 5: ESP32­C3 Family Flash Circuit
C12
C2
0.1uF
TBD
GND
R2 499
XTAL_P
24 R3 0
SPIQ
23 R4 0
SPID
22 R5 0
21
3
20 R6 0
SPIWP SPIWP
19 19 R7 R7 0 0
SPIHD
18
17
C10 C11
0.1uF 1uF
GND GND
Figure 6: Schematic for ESP32­C3 Family's Crystal
C12
0.1uF
GND
TBD
XTAL_P
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SPIQ
SPID
SPICLK
SPICS0
SPIWP SPICS0
SPIHD
SPICLK
VDD_SPI
SPIHD
VDD33
VDD33
If using ESP32-C3FN4 or ESP32-C3FH4,
flash is not mounted.
U0TXD
U0RXD
GPIO19
GPIO18
SPIQ
SPID
SPICLK
SPICS0
SPIWP SPICS0
SPIHD SPIHD
SPICLK
VDD_SPI
SPIHD
VDD33
VDD33
If using ESP32-C3FN4 or ESP32-C3FH4,
external flash could be removed.
9
VDD_SPI
1 5
/CS DI
6 2
CLK DO
7 3
/HOLD /WP
U3 FLASH-3V3
2
GND
VDD_SPI
2
1 5 SPID
/CS /CS DI DI
6 2 SPIQ
CLK DO
7 3 SPIWP
/HOLD /WP
U3 FLASH-3V3
GND
ESP32-C3 Family Hardware Design Guidelines V0.5
SPID
SPIQ
SPIWP
1
1