Espressif Systems ESP32-C3 Series Hardware Design Manuallines page 22

3 PCB Layout Design
3.5 RF
In a four-layer PCB design, the RF trace is highlighted in pink in Figure 18.
Figure 18: ESP32­C3 Family RF Layout in a Four­layer PCB Design
• The RF trace should have 50 Ω single-ended characteristic impedance. The reference plane is the second
layer. A π-type matching circuit should be reserved on the RF trace and placed close to the chip.
• The RF trace should have consistent width and not branch out. It should be as short as possible with
dense ground vias around for inteference shielding.
Espressif Systems
Figure 17: ESP32­C3 Family Crystal Layout
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ESP32-C3 Family Hardware Design Guidelines V0.5