Samsung S3C9444 User Manual page 140

BASIC TIMER and TIMER 0
MUX
X
DIV
IN
R
Bit 0
R
DIV
X
IN
NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval
(until bit 4 the basic timer counter is set).
10-10
Bit 1
Bits 3, 2
Clear
1/4096
8-Bit Up Counter
1/1024
(BTCNT, Read-Only)
MUX
1/128
Bits 7, 6
1/4096
1/256
MUX
1/8
1
Figure 10-7. Basic Timer and Timer 0 Block Diagram
RESET or
STOP
Basic Timer Control Register
(Write '1010xxxxB' to disable.)
Data Bus
When BTCNT.4 is set after
releasing from RESET or STOP
mode, CPU clock starts.
Data Bus
T0CNT (D0H)
(Read-Only)
8-Bit Comparator
T0DATA Buffer
T0DATA (D1H)
(Read/Write)
Data Bus
S3C9444/F9444_UM_REV1.10
OVF
Clear Bit 3
Bit 1
Match
Bit 0
Bit 3
Match Signal
Basic Timer Control Register
Timer 0 Control Register
RESET
IRQ0