Digital Input/Output; Interrupts - Measurement Computing PCI-DAS6402/16 User Manual

PCI-DAS6402/16 User's Guide

Digital input/output

Table 13. Digital input/output specifications (main connector)
Digital type (main connector)
Configuration
Output high voltage (IOH = -0.4 mA)
Output low voltage (IOL = 8 mA)
Input high voltage
Input low voltage
Digital type (digital I/O connector)
Number of I/O
Configuration
Input high voltage
Input low voltage
Output high voltage (IOH = -2.5 mA)
Output low voltage (IOL = 2.5 mA)
Power-up / reset state
SSH output
SSH polarity

Interrupts

Interrupts PCI INTA# - mapped to IRQn via PCI BIOS at boot-time
Interrupt enable Programmable through PLX9080
ADC interrupt sources DAQ_ACTIVE:
(sw programmable)
DAQ_STOP:
DAQ_DONE:
DAQ_FIFO_1/4_FULL:
DAQ_SINGLE:
DAQ_EOSCAN:
DAQ_EOSEQ:
DAC interrupt sources DAC_ACTIVE:
(sw programmable) DAC_DONE:
DAC_FIFO_1/4_EMPTY:
DAC_HIGH_CHANNEL:
DAC_RETRANSMIT:
External interrupt Interrupt is generated via edge-sensitive transition on the External Interrupt pin. Rising/falling
edge polarity software selectable.
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Output: 74LS175
Input: 74LS244
4 inputs, 4 outputs (DIN0 through DIN3; DOUT0 to DOUT3)
2.7 V min
0.5 V max
2.0 V min, 7 volts absolute max
0.8 V max, –0.5 volts absolute min
Table 14. Digital input/output specifications (DIO connector)
82C55
24 (FIRSTPORTA Bit 0 through FIRSTPORTC Bit 7)
! 2 banks of 8 and 2 banks of 4 or
! 3 banks of 8 or
! 2 banks of 8 with handshake
2.0 V min, 5.5 V absolute max
0.8 V max, –0.5 V absolute min
3.0 V min
0.4 V max
Input mode (high impedance)
Table 15. Simultaneous sample and hold specifications
TTL-compatible output, HOLD is asserted from start of the conversion for
Channel 0 through conversion of the last channel in the scan. Available at user
connector (SSH OUT / D/A PACER OUT). This pin is software selectable as
SSH OUT or D/A PACER OUT.
HOLD high (default) or HOLD low, software selectable
Table 16. Interrupt specifications
Interrupt is generated when a DAQ sequence is active.
Interrupt is generated when A/D Stop Trigger In is detected.
Interrupt is generated when a DAQ sequence completes.
Interrupt is generated when ADC FIFO is ¼ full.
Interrupt is generated after each conversion completes.
Interrupt is generated after the last channel is converted in multi-
channel scans.
Interrupt is generated after each interval delay during multi-
channel scans.
Interrupt is generated when DAC waveform circuitry is active.
Interrupt is generated when a DAC sequence completes.
Interrupt is generated DAC FIFO is ¼ empty.
Interrupt is generated when the DAC high channel output is
updated.
Interrupt is generated when the end of a waveform sequence has
occurred in retransmit mode.
5-6
Specifications