Accuracy Components; Analog Output Pacing And Triggering - Measurement Computing PCI-DAS6402/16 User Manual

PCI-DAS6402/16 User's Guide
Range Typical accuracy
±10.000 V ±3.5 LSB
±5.000 V ±3.5 LSB
0 to +10.00 V ±3.5 LSB
0 to +5.000 V ±3.5 LSB

Accuracy components

Range Gain error (LSB)
±10.000 V ±2.0 max, ±1.5 typ
±5.000 V ±2.0 max, ±1.5 typ
0 to +10.00 V ±2.0 max, ±1.5 typ
0 to +5.000 V ±2.0 max, ±1.5 typ
Each PCI-DAS6402/16 is tested at the factory to assure the board's overall error does not exceed ±4.0 LSB.
Total analog output error is a combination of gain, offset, integral linearity, and differential linearity error. The
theoretical worst-case error of the board may be calculated by summing these component errors. Worst case
error is realized only in the unlikely event that each of the component errors are at their maximum level, and
causing error in the same direction. Although an examination of the chart and a summation of the maximum
theoretical errors shows that the board could theoretically exhibit a ±6.0 LSB error, our testing assures this error
is never realized in a board that we ship.
Typical accuracy is derived directly from the various component typical errors. This typical, maximum error
calculation for the PCI-DAS6402/16 yields ±3.5 LSB. However, this again assumes that each of the errors
contributes in the same direction and the ±3.5 LSB specification is quite conservative.

Analog output pacing and triggering

D/A pacing Internal counter – ASIC
(SW programmable)
External source (D/A external pacer)
Software paced
! External digital (external D/A trigger/pacer gate)
D/A gate sources
! External analog (analog trigger in)
(SW programmable)
! External digital: Programmable, active high or active low, level or edge
D/A gating modes
! External analog: Software-configurable for above or below reference. Gating levels set by
D/A trigger sources External digital (external D/A trigger/pacer gate)
Software triggered
D/A triggering modes External digital: Software-configurable for rising or falling edge.
! From 16k RAM buffer via DMA (demand or non-demand mode) using scatter gather.
Data transfer
! Programmed I/O
! Update DACs individually or simultaneously (SW selectable)
Throughput 100 kHz max per channel, 2 channels simultaneous
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Table 10. Typical accuracy specifications
Table 11. Accuracy component specifications
Offset error (LSB)
±2.0 max, ±1.0 typ
±2.0 max, ±1.0 typ
±2.0 max, ±1.0 typ
±2.0 max, ±1.0 typ
Table 12. Analog output pacing and triggering specifications
DAC0 or DAC1
5-5
DLE (LSB) ILE (LSB)
±1.0 max, ±0.5 typ ±1.0 max, ±0.5 typ
±1.0 max, ±0.5 typ ±1.0 max, ±0.5 typ
±1.0 max, ±0.5 typ ±1.0 max, ±0.5 typ
±1.0 max, ±0.5 typ ±1.0 max, ±0.5 typ
Specifications