Digital Input / Output; Interrupts - Measurement Computing PCI-DAS4020/12 User Manual

PCI-DAS4020/12 User's Guide
Total analog output error is a combination of gain, offset, integral linearity, and differential linearity
error. The overall absolute worst-case error of the board may be calculated by summing these component
errors. Worst case error is realized only in the unlikely event that each of the component errors are both at
their maximum level, and causing error in the same direction. Though this is very uncommon, it is still
possible.
Monotonicity Guaranteed monotonic over temperature
Analog output ±0.11 LSB/°C max, all ranges
drift
Settling time 5µs max
(20 V step to ± ½
LSB)
Slew rate 5 V/µs
Current drive ±5 mA
Output short- 25 mA indefinite
circuit duration
Output coupling DC
Output 0.5 Ohm max
impedance
Miscellaneous Single buffered output latch
Update DACs individually
On power-up and reset, the inputs to both D/A output buffers are grounded and the board's D/A
outputs will be set to 0 volts ± 6 mV. Upon writing to the D/A converters, the output buffers
will reflect the D/A outputs and achieve rated accuracy. However, upon writing a 0 to the
D/A's, a small output change may be noted (up to 10 LSB).

Digital input / output

Digital type (40-pin connector)
Configuration
Number of channels
Output high
Output low
Input high
Input low
Power-up / reset state

Interrupts

Interrupts
Interrupt enable
ADC Interrupt sources
External
External Interrupt Enable
Table 6-10. DIO specifications
8255A
2 banks of 8, 2 banks of 4, programmable by bank as input or output
24 I/O
3.0 volts min @ 2.5 mA
0.4 volts max @ 2.5 mA
2.0 volts min, Vcc + 0.5 volts absolute max
0.8 volts max, GND − 0.5 volts absolute min
Input mode (high impedance)
Table 6-11. Interrupt specifications
INTA# - mapped to IRQn via PCI BIOS at boot-time
Software programmable
DAQ_ACTIVE: Interrupt is generated when a DAQ sequence is active.
DAQ_STOP: Interrupt is generated when A/D Stop Trigger In is detected.
DAQ_DONE: Interrupt is generated when a DAQ sequence completes.
DAQ_FIFO_1/2_FULL:
Interrupt is generated when ADC FIFO is ½ full.
DAQ_SINGLE: Interrupt is generated after each conversion completes.
Interrupt is generated via edge-sensitive transition on the Interrupt In pin on the 40-
pin connector. Rising/falling edge polarity selection. The Interrupt In pin is pulled up
to 5 V through a 10 K resistor.
Active low Interrupt Enable signal on the 40-pin connector. The Interrupt Enable pin
is pulled up to 5 V through a 10 K resistor.
6-4
Specifications