Quectel BG96-NA Hardware Design page 39

The logic levels are described in the following table.
Table 13:Logic Levels of Digital I/O
Parameter
V
IL
V
IH
V
OL
V
OH
The module provides 1.8V UART interface. A level translator should be used if your application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instrument is
recommended. The following figure shows a reference design.
Please visit http://www.ti.comformore information.
Another example with transistor translation circuit is shown as below. Thecircuitdesign of dotted line
section can refer to the circuitdesign of solid line section, in terms of both module input and output circuit
designs, but please pay attention to the direction of connection.
BG96-NA_Hardware_Design
Min.
-0.3
1.2
0
1.35
Figure 18: Reference Circuit with Translator Chip
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BG96-NA Hardware Design
Max.
0.6
2.0
0.45
1.8
LTE Module Series
Unit
V
V
V
V