Synthesised Local Oscillator - Tait T880 II Series Adjustment Manual

M880-00
2.3

Synthesised Local Oscillator

(Refer to the synthesiser circuit diagram (sheet 7) and the VCO circuit diagram (sheet 3)
in Section 6.2.)
FREQUENCY SYNTHESISER IC
12.8MHz
Reference Fixed Reference
Oscillator Divider
/64
f
ref
Ref
Phase
Mod Modulator
Clk
Data
Serial
Controller
Bus
En
The synthesiser (IC740) employs a phase-locked loop (PLL) to lock a voltage controlled
oscillator (VCO) to a given reference frequency. The synthesiser receives the divider
information from the control microprocessor via a 3 wire serial bus (clock, data, enable).
When the data has been latched in, the synthesiser processes the incoming signals from
the VCO buffer (f
in
A reference oscillator at 12.8MHz (=IC700) is buffered (IC710 pins 5 & 6) and divided
down to 200kHz (IC730). This 200kHz square wave is then summed with the modulat-
ing audio and passed to an integrator (IC720 pins 13 & 12, Q710, Q720). This produces a
ramping waveform which is centred around a DC level determined by the incoming
audio. IC720 pins 10 & 11 perform as a comparator, ultimately producing a phase-mod-
ulated 200kHz square wave. This is followed by another phase shifting stage (IC720
pins 8 & 9, Q730, Q740), before being divided down to 6.25kHz or 5kHz within the syn-
thesiser IC (IC740).
A buffered output of the VCO (Q795) is divided with a prescaler and programmable
divider which is incorporated into the synthesiser chip (IC740). This signal is compared
with the phase modulated reference signal at the phase detector (also part of the synthe-
siser chip). The phase detector outputs drive a balanced charge pump circuit (Q760,
Q770, Q775, Q780, Q785) and active loop filter (IC750 pins 5, 6 & 7, Q790) which pro-
duces a DC voltage between 0V and 20V to tune the VCO. This VCO control line is fur-
ther filtered to attenuate noise and other spurious signals. Note that the VCO frequency
increases with increasing control voltage.
If the synthesiser loop loses lock, a pulsed signal appears at LD (pin 2) of IC740. This
signal is filtered and buffered by IC750 pins 1, 2 & 3, producing the Lock-Detect signal
used to shut off the power supply to the drive amplifier. IC750 pin 1 is at 20V when the
synthesiser is out of lock.
Copyright TEL
Phase Charge
Divider Detector
Pump
/R
Programmable
Divider
/N
Figure 2.3 T881 Synthesiser Block Diagram
) and the phase modulator (f
T881 Circuit Operation
VCO
Modulation
Loop
Filter
VCO
Σ
Prescaler
64/65
f
in
).
ref
C2.5
VCO PCB
Output
Buffer Buffer
+22dBm
L.O.
Divider Buffer
10/07/00