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If the host PC is not able to provide the requested current, the enumeration fails. Therefore, the STMPS2151STR
remains OFF and the 5 V power reference of the board is OFF. The 5 V Green LED LD7 is turned OFF.
The Green LED LD7 is turned ON when the B-G474E-DPOW1 product is powered by the 5V correctly. The COM
LED LD9 indicates the STLINK-V3E communication status with the host, refer to Overview of ST-LINK derivatives
technical note (TN1235).
Note:
In case the board is powered by a USB wall charger on CN3 with JP5 on STLK, there is no USB enumeration, so
the COM LED LD9 remains OFF, but the power switch is activated and the board is powered up, with 700 mA
current protection.
9.1
STLINK-V3E deactivation (Reset mode)
It is simple to deactivate the STLINK-V3E function, by adding a jumper on JP6 to connect STLK NRST to
GND, as shown in
impossible in this Reset state, where all STLINK-V3E PIOs are in high impedance.
The Reset state is useful to connect external probe onto CN1 debug or CN10 TAG connectors for embedded
STM32 debug.
In this Reset state, if JP7 is OFF, 5V selection JP5 CHGR source can be used to power the board with no current
protection, but 5V selection JP5 STLK is not functional.
Reference
(2)
JP6
1. The default setting is in bold.
2. In case JP6 is ON, JP7 must be OFF.
9.2
STLINK-V3E physical disconnection
It is possible to physically isolate partially or completely the STLINK-V3E signals from the rest of the
STM32 board by disconnecting part of physical signals or all of them:
•
By default, STLINK-V3E is physically connected to STM32: SW1 is in 'ALL ON' low physical position, and
JP7 is ON, to enable the use of STLINK-V3E in Program/Debug/Monitoring modes. Refer to
Table
4, and
•
In case of complete physical isolation, Octal Mechanical switch SW1 must be set in 'ALL OFF' and JP7 must
be OFF. The CN3 STLINK-V3E connector behaves like an external power supply with 5V selection coming
from either CHGR or STLK source. Program/Debug/Monitoring through ST-LINK are not possible.
•
In case of partial signal connection is chosen, ensure the ST-LINK firmware and STM32 Target Software are
compatible with your selected SW1 / JP7 configuration.
UM2577 - Rev 2
Figure 8
and
Table
3. Programming, debugging, and monitoring through ST-LINK are
Figure 8.
JP6 STLK NRST default configuration
Table 3.
(1)
Function
Jumper
OFF
STLINK-V3E active
ON
STLINK-V3E Reset state
Table 5
for a detailed description.
JP6 STLK NRST configuration
STLINK-V3E detects USBSTLK plug on CN3
Set STLINK-V3E in Reset mode (All IOs in high impedance)
UM2577
STLINK-V3E deactivation (Reset mode)
Comment
Figure
9,
page 15/54
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