A0 And A1 Address Combinations; A2 And A3 Address Combinations; Commonly-Used Address Combinations - Texas Instruments DAC8728EVM User Manual

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4.9 SN74LVC139 Outputs
Table 6 through Table 8
correspond to the signals from the J1 header.
A1
0
0
1
1
A3
0
0
1
1
4.10 BUSY Signal
The BUSY signal is routed to an interrupt on the host processor; this allows the user to monitor the state
of the correction engine. The BUSY pin is pulled low when the correction engine runs, and is pulled high
by an external pull-up when the correction process completes.
SBAU161 – February 2010
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show the truth tables for the outputs of the SN74LVC139. Note that A3 to A0
Table 6. A0 and A1 Address Combinations
A0 RST
0 1
1 1
0 1
1 0
Table 7. A2 and A3 Address Combinations
A2 LDAC
0 1
1 1
0 1
1 0
Table 8. Commonly-Used Address Combinations
Open1 + LATCH_CTRL
DC_CS + R/W
LDAC + LATCH_CTRL
DC_CS + Open2
Copyright © 2010, Texas Instruments Incorporated
CLR R/W
1 1
1 0
0 1
1 1
DC_CS2 DC_CS1
1 1
1 0
0 1
1 1
A3 to A0 (Hex)
0x0
0x5
0xC
0x7
Parallel Control
LATCH_CTRL
0
1
1
1
DC_CS0
0
1
1
1
DAC8728EVM
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