Renesas SH7262 Series Hardware Design Manual
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Renesas SH7262 Series Hardware Design Manual

Renesas SH7262 Series Hardware Design Manual

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SH7262/SH7264 Group
Hardware Design Guide
Summary
This application note contains tips on designing a system using the SH7264. As a technical reference it will help the
designer avoid common mistakes and get their product up and running when doing their first SH2A design.
Target Device
SH7262/SH7264 MCU (In this document, SH7262/SH7264 are described as "SH7264".)
Contents
1.
Power Supplies ................................................................................................................................. 2
2.
Reset ................................................................................................................................................. 7
3.
Oscillator Circuit .............................................................................................................................. 10
4.
Operating Mode Control.................................................................................................................. 12
5.
External ROM.................................................................................................................................. 17
6.
Handling of Pins .............................................................................................................................. 21
7.
On-chip Resource Access............................................................................................................... 26
8.
Endianness...................................................................................................................................... 27
9.
Power-down Modes......................................................................................................................... 28
10. References ...................................................................................................................................... 34
Related Application Notes
For more information, refer to the following application notes:
• SH7262/SH7264 Group Guidelines for Hi-Speed USB 2.0 Board Design
• SH7262/SH7264 Group Using Deep Standby Mode in Power-down Mode
• SH7262/SH7264 Group Connecting the NOR Flash Memory
• SH7262/SH7264 Group Interfacing Serial Flash Memory Using the Renesas Serial Peripheral Interface
About Active-low Pins (Signals)
The symbol "#" suffixed to the pin (or signal) names indicates that the pins (or signals) are active-low.
REJ06B0999-0100 Rev. 1.00
Jun. 30, 2010
APPLICATION NOTE
REJ06B0999-0100
Rev. 1.00
Jun. 30, 2010
Page 1 of 36

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Summary of Contents for Renesas SH7262 Series

  • Page 1: Table Of Contents

    • SH7262/SH7264 Group Using Deep Standby Mode in Power-down Mode • SH7262/SH7264 Group Connecting the NOR Flash Memory • SH7262/SH7264 Group Interfacing Serial Flash Memory Using the Renesas Serial Peripheral Interface About Active-low Pins (Signals) The symbol "#" suffixed to the pin (or signal) names indicates that the pins (or signals) are active-low.

  • Page 2: Power Supplies

    SH7262/SH7264 Group Hardware Design Guide Power Supplies Power Supplies CPU core voltage is between 1.1 V and 1.3 V, and I/O power supply voltage is between 3.0 V and 3.6 V. This LSI (SH7264) uses both digital and analog power supplies. Place the digital circuit and analog circuit as far as possible on the board.
  • Page 3 SH7262/SH7264 Group Hardware Design Guide Table 2 Analog Power Supplies Symbol Name Voltage Range Description PLLVcc PLL power supply 1.1 to 1.3 V Power supply for internal PLL oscillator PLLVss PLL ground Ground pin for internal PLL oscillator (2) (4) USBAPVcc 3.0 to 3.6 V Power supply for USB pins...
  • Page 4 SH7262/SH7264 Group Hardware Design Guide Signal lines prohibited Power supply PLLVcc PLLVss Note: When designing the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interferences.
  • Page 5 SH7262/SH7264 Group Hardware Design Guide Bypass Capacitor A multilayer ceramic capacitor must be installed as a bypass capacitor for each pair of power supply pins. Install the bypass capacitor as close as possible to the LSI power supply pins. Connect the bypass capacitor with capacitance between 0.1 and 0.33 µF (recommended value).
  • Page 6 SH7262/SH7264 Group Hardware Design Guide AVcc AVref AVss PVcc USBUVss USBUVcc USBAVss USBAVcc USBAPVss USBAPVcc REFRIN USBDVss USBDVcc VBUS USBDPVss PVcc USBDPVcc ASEMD PLQP0208KB-A USB_X2 Top view USB_X1 PVcc PD15 PD14 PD13 PD12 PD11 PD10 PVcc RTC_X2 RTC_X1 PVcc XTAL EXTAL PVcc PLLVss...

  • Page 7: Reset

    RES# pin exceeds the V voltage. Figure 4 shows the relation between power-on/off and clock, reset signals. This timing is easily accommodated by many "supervisor" ICs available on the market such as Renesas Electronics RNA51957BFP. Stability oscillation period Normal operation period...
  • Page 8 SH7262/SH7264 Group Hardware Design Guide Power-on Reset The SH7264 has two reset options; power-on reset and manual reset. This section describes sources for the power-on reset exception handling. 2.3.1 Power-on Reset by the RES# Pin When the RES# pin is driven low, the SH7264 enters power-on reset state to initialize the CPU’s internal state and all (note) on-chip peripheral registers .
  • Page 9 SH7262/SH7264 Group Hardware Design Guide Reset input (Low active) Reset signal to WDTOVF entire system (Low active) Figure 5: System Reset using WDTOVF# REJ06B0999-0100 Rev. 1.00 Page 9 of 36 Jun. 30, 2010...

  • Page 10: Oscillator Circuit

    SH7262/SH7264 Group Hardware Design Guide Oscillator Circuit Clock Pins Pins listed in the following table can be connected to crystal resonators or input clocks. Table 3 Clock pins Xin Pin Xout Pin Remarks (Crystal resonator can be (Crystal resonator can be connected) connected, or used as external clock input pin)
  • Page 11 SH7262/SH7264 Group Hardware Design Guide Connecting a Crystal resonator Figure 7 shows an example of connecting a crystal resonator to the SH7264. Place the crystal resonator and capacitors (CL1 and CL2) as close to pins Xin and Xout as possible. To avoid inductance and to allow the crystal resonator to oscillate accurately, use the points when the capacitors area connected to the crystal resonator in common and do not place wiring patters close to these components.

  • Page 12: Operating Mode Control

    Boot Mode Boots the MCU from the memory connected to CS0 space (Boot mode 0) Boots the MCU from serial flash memory connected to the Renesas Serial Peripheral Interface channel 0 at high speed (Boot mode 1) Boots the MCU from NAND flash memory connected to the NAND flash...
  • Page 13 Boot modes 1 and 3 allow the engineer to boot the SH7264 from serial flash memory which is connected to channel 0 of the Renesas Serial Peripheral Interface (RSPI). This section describes boot modes 1 and 3. Steps 1 and 2 are initiated (note) by the MCU in SPI boot mode, step 3 (optional) is a function of the “loader”...
  • Page 14 SH7262/SH7264 Group Hardware Design Guide 4.1.4 Boot Mode 2 Boot mode 2 allows the engineer to boot the SH7264 from NAND flash memory which is connected to the SH7264 NAND flash memory controller. The SH7264 supports the large-block (2048 bytes + 64 bytes) NAND flash memory with 5-byte address cycles (bigger than 2 Gb density).
  • Page 15 SH7262/SH7264 Group Hardware Design Guide Clock Operating Modes 4.2.1 External Pins Setting to Decide Clock Operating Modes When the RES# pin is driven low, the SH7264 uses external pins to decide clock operating modes. Table 5 lists the relationship between external pins and clock operating modes. Table 5 Relationships between External Pins and Clock Operating Modes Mode Pin Combination...
  • Page 16 SH7262/SH7264 Group Hardware Design Guide 4.2.6 Available Clock Frequency Range Table 6 lists clock operating modes and available clock frequency range; do not set these pins other than the combinations shown in the table below. Table 6 Relationship between Clock Operating Mode and Clock Frequency Range Clock FRQCR Ratio of...

  • Page 17: External Rom

    SH7262/SH7264 Group Hardware Design Guide External ROM NOR Flash Memory Figure 10 shows an example of NOR flash memory circuit. For more information, refer to the application note "SH7262/SH7264 Group Connecting the NOR Flash Memory". 3.3 V NOR Flash Memory SH7264 3.3 V 3.3 V...
  • Page 18 Hardware Design Guide Serial Flash Memory Connect the serial flash memory to the SH7264 internal Renesas Peripheral Interface (RSPI). Figure 11 shows an example of serial flash memory circuit. Set the SH7264 pin functions as shown in Table 7. For more information, refer to the application note "SH7262/SH7264 Group Interfacing Serial Flash Memory Using the Renesas Serial Peripheral Interface".
  • Page 19 SH7262/SH7264 Group Hardware Design Guide NAND Flash Memory Figure 12 shows an example of NAND flash memory circuit. Set the SH7264 pin functions as shown in Table 8. NAND Flash Memory K9F2G08U0A SH7264 256 MB 8-bit I/O7 to I/O0 NAF7 to NAF0 3.3 V 3.3 V 3.3 V FCE#...
  • Page 20 SH7262/SH7264 Group Hardware Design Guide Table 8 Multiplexed Pins SH7264 Port Control Register Peripheral SH7264 Pin Name Multiplexed Pin Name Register Function MD Bit Setting Name NAND Flash NAF4 to NAF7 PDCR3 PD15MD[1:0] = B'01 PD15/D15/NAF7/PWM2H Memory PD14MD[1:0] = B'01 PD14/D14/NAF6/PWM2G Controller PD13MD[1:0] = B'01...

  • Page 21: Handling Of Pins

    SH7262/SH7264 Group Hardware Design Guide Handling of Pins ASEMD0# Pin The ASEMD0# pin selects the H-UDI related functions for use by the emulator. If the input signal to the ASEMD0# pin is low during the RES# assertion the SH7264 will enter ASE mode. If the input signal is high during the RES# assertion, the MCU will enter product-chip mode (normal operation).
  • Page 22 SH7262/SH7264 Group Hardware Design Guide PVcc = I/O power supply All pins must be pulled up by resistors with 4.7 kΩ or greater. PVcc PVcc PVcc 36-pin H-UDI port connector Target MCU AUDCK AUDCK AUDATA0 AUDATA0 AUDATA1 AUDATA1 AUDATA2 AUDATA2 AUDATA3 AUDATA3 AUDSYNC...
  • Page 23 SH7262/SH7264 Group Hardware Design Guide PVcc = I/O power supply All pins must be pulled up by resistors with 4.7 kΩ or greater. PVcc PVcc PVcc PVcc PVcc PVcc Target MCU 14-pin H-UDI port connector (GND) TRST TRST ASEBRKAK ASEBRKAK/ASEBRK /ASEBRK N.C.
  • Page 24 SH7262/SH7264 Group Hardware Design Guide 6.4.2 Analog Pin Protection Circuit As shown in Figure 15, connect the protection circuit between AVcc and AVss to prevent damage due to an abnormal voltage, such as an excessive surge at analog input pins (AN0 to AN7) and analog reference voltage (AVREF). The circuit also is used as the RC filter to minimize the noise.
  • Page 25 SH7262/SH7264 Group Hardware Design Guide USB Pins For details on handling pins to use the USB 2.0 host or function module (USB module), refer to the application note "SH7262/SH7264 Group Guidelines for Hi-Speed USB 2.0 Board Design". Terminating Pins 6.6.1 Unused Pins Table 9 lists the handling of unused pins.

  • Page 26: On-Chip Resource Access

    SH7262/SH7264 Group Hardware Design Guide On-chip Resource Access The SH7264 includes the high-speed internal RAM, large-capacity internal RAM, and on-chip peripheral modules as the on-chip resources. The number of cycles to access the high-speed internal RAM varies according to the bus used. For details on buses connected to on-chip resources, refer to Figure 1.3 Block Diagram in the SH7262 Group, SH7264 Group Hardware Manual.

  • Page 27: Endianness

    SH7262/SH7264 Group Hardware Design Guide Endianness The SH7264 supports big-endian order to store the most significant byte (MSB) at the lowest address 0, and little- endian order to store the least significant byte (LSB) at the lowest address 0. The default endianness is big-endian after power-on reset on all areas.

  • Page 28: Power-Down Modes

    SH7262/SH7264 Group Hardware Design Guide Power-down Modes The SH7264 has the following power-down modes and function. (1) Sleep mode (2) Software standby mode (3) Deep standby mode (4) Module standby function As power-down modes stop CPU, clock, internal memory, and some peripherals or turns off the power supply, it will reduce power consumption.
  • Page 29 SH7262/SH7264 Group Hardware Design Guide Sleep Mode In sleep mode, only CPU stops its operation. When executing the SLEEP instruction while the STBY bit in the Standby control register 1 (STBCR1) is 0, the SH7264 transitions from the program execution state to sleep mode. The CPU stops its operation immediately after executing the SLEEP instruction;...
  • Page 30 SH7262/SH7264 Group Hardware Design Guide Pin States in Power-down Modes 9.5.1 Pin States in Sleep Mode As the peripheral modules operate in sleep mode, the pin state varies according to the operation of peripheral modules. 9.5.2 Pin States in Module Standby Mode When using module standby function for the module specified as general-purpose I/O port, the pins of the module whose registers to be initialized at the module standby function is configured to default state.
  • Page 31 SH7262/SH7264 Group Hardware Design Guide Table 14 Pin States in Software Standby Mode and Deep Standby Mode (2/3) Pin Name Description Other AUDIO_XOUT (only the MCU with 640-KB Specified by the HIZ bit (STBCR3 register) output RAM) 1: High impedance state pins, I/O DACK1, DACK0, TEND1, TEND0, 0: Pin state is retained for output pin and I/O...
  • Page 32 SH7262/SH7264 Group Hardware Design Guide Table 15 Pin States in Software Standby Mode and Deep Standby Mode (3/3) Pin Name Description Input pins EXTAL Clock Software Deep standby operating standby mode mode mode 0, 2 Input state Hi-Z (Input state when the RCKSEL is 1) 1, 3 Hi-Z...
  • Page 33 SH7262/SH7264 Group Hardware Design Guide 9.5.4 Pin States after Waking Up from Deep Standby Mode After waking up the MCU from deep standby mode, pin states are retained until the IOKEEP bit in the DSFR register is cleared by 0. However, when the EBUSKEEPE bit is set to 0, external memory control pin states are released immediately after waking up the MCU from deep standby mode.

  • Page 34: 10. References

    10. References • Software Manual SH-2A, SH2A-FPU Software Manual Rev.3.00 The latest version of the software manual can be downloaded from Renesas Electronics website. • Hardware Manual SH7262 Group, SH7264 Group Hardware Manual Rev.2.00 The latest version of the hardware manual can be downloaded from Renesas Electronics website.
  • Page 35 SH7262/SH7264 Group Hardware Design Guide Website and Support Renesas Technology Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry All trademarks and registered trademarks are the property of their respective owners. REJ06B0999-0100 Rev. 1.00 Page 35 of 36 Jun. 30, 2010...
  • Page 36 SH7262/SH7264 Group Hardware Design Guide Revision Record Description Rev. Date Page Summary 1.00 Jun.30.10 — First edition issued REJ06B0999-0100 Rev. 1.00 Page 36 of 36 Jun. 30, 2010...
  • Page 37 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
  • Page 38 Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific"...

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