Table of Contents
Advertisement
PLL/Modulation Options Screen
-
-
3.4 PLL/Modulation Options Screen
The PLL/Modulation Options screen is accessed by pressing the PLL/Modula-
tion Option button, located on the chip layout screen, and is displayed as
shown in Figure 3–3:
Figure 3–3. PLL/Modulation Options Screen
The PLL/Modulations Options screen is divided into four sections:
-
-
The user can select FSK Modulation. The FSK Test button, located on the
chip layout screen, will allow the user to transmit data using the TRF6900.
Options for use with the FSK Test button are the pulse repetition frequency
(PRF), which is defaulted to 100 Hz, and the Run Time (Min), which can
be set in minutes. For example, if you want the test to run for five minutes,
set Run Time (Min) to 5.
The PLL/Modulation Options button brings up the PLL/Modulation Op-
tions screen as shown in Figure 3–3. This button is activated only when
the PLL is on.
APLL
Controls the acceleration factor for the PLL. The values are 0, 20, 40, 60,
80, 100, 120, and 140. Any changes are automatically updated in the PLL
and MM Options section of the main program screen, after pressing the
Send Bits button located on the PLL screen.
NPLL
Controls the N-Divider of the PLL. The NPLL can be set to either 256 or
512. Any changes are automatically updated in the NPLL box on the main
program screen, after pressing the Send Bits button located on the PLL
screen.
DV6 Display
Set to 1 by
Double Clicking
f
Frequency
1
915 MHz
f
Frequency
2
915.10 MHz
FSK Deviation
of 100 kHz
Send Bits
Button
Advertisement
Table of Contents
