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About This Manual This document is intended to introduce the TRF6900 evaluation module (EVM) and familiarize the reader with setting up and testing the TRF6900 EVM using the evaluation software in a typical laboratory environment. How to Use This Manual This document contains the following chapters: Chapter 1 –...
TRF6900. Step 2: Copy the TRF6900.exe file to the hard drive. Step 3: Connect a DB25 female to DB25 male cable between the TRF6900 evaluation board and the PC parallel port. The DB25 female end of the cable is connected to the TRF6900.
2.3 EVM DC Voltage Setup The evaluation board should be used with a dc power supply voltage of 8 V nominal. Figure 2–1 details the dc voltage supply setup for the TRF6900 EVM. Figure 2–1. TRF6900 EVM DC Voltage Setup V out for LM317 voltage regulator is equal to: V out = 1.25(1+(R44/R43))
Initialize Printer PC Output Select Input PC Output Note: The TRF6900 EVM uses pins 2 – 7 for signals from the PC to the EVM. Pins 11 and 12 are used for signals from the EVM to the PC. Evaluation Board...
Jumper Connections 2.6 Jumper Connections Figure 2–3 shows the default position of the jumpers on the TRF6900 EVM. Figure 2–3. EVM Jumper Locations and Default Configuration of the EVM J1 MIX_OUT J3 IF Out MIX_OUT IF1_OUT BPF1 Input BPF1 BPF2 Input...
Default is a 0.1 µF-Capacitor (C3) 2.6.2 Jumper Description The jumpers on the TRF6900 EVM, as shown in Figure 2–3, are used for the following purposes: Jumper JP1 is used for testing of the mixer circuit of the TRF6900. Testing of the mixer stage by itself is accomplished by connecting JP1–1 to JP1–2,...
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Jumper Connections Jumper JP2 is used for testing of the mixer circuit of the TRF6900. Testing of the mixer stage by itself is accomplished by connecting JP1–1 to JP1–2, JP2–1 to JP2–3, and removing the 0.1-µF capacitor connecting terminal 44 (MIX_OUT) and terminal 42 (IF1_IN). The IF mixer and LNA stages may be tested together by connecting JP1–1 to JP1–2, JP2–2 to JP2–3...
PLL circuit. AMP_OUT TP The AMP_OUT test point is used to monitor the output of the LPF amplifier/post-detection amplifier. LDET TP The LDET test point is used to monitor the lock detect line of the TRF6900. Evaluation Board...
The TXDATA test point is used to monitor the transmitted data. Transmit data from an external source can also be applied at this point. 2.7.3 Adjustments Resistor R44 is varied to adjust the VCC1 voltage applied to IC1 (TRF6900). 2.7.4 LED Indicators VCC LED If JP8 is installed, the VCC LED is illuminated when voltage is applied to IC1.
Chapter 3 Software User’s Guide This chapter describes the Windows-based software application that accom- panies the EVM. Topic Page Introduction ..........3–2 Main Program Screen .
However, if the operating system is Windows 95/98, the software application can run on its own. Both the Windows NT Driver and the TRF6900 software are provided on dis- kette. Your system administrator must install the Windows NT Driver if you do not have administrative privileges on your computer.
Left Mouse Button to Obtain Frequency Chip Layout View Press to Program the TRF6900 Computer Printer Port LPT1 or LPT2 NOTE: When word bits are displayed in RED, the Send Words Now (F12) button on the main program screen, must be pressed for changes to be updated.
Main Program Screen 3.2.2 Mode Options This section allows the user to control various features of the TRF6900. The following is a brief summary of the 12 controls. 1) PLL: Turns the phase-locked loop on or off. 2) VCO: Turns the voltage controlled oscillator on or off.
F12 on the keyboard, sends all the words to the TRF6900. 3.2.8 Operation Mode Operation Mode shows if the TRF6900 is enabled, which mode (0 or 1) is se- lected, and if the transmit (TX) data line is on or off. 3.2.9...
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Click the arrow beside the box to turn LNA off, set to High Gain mode, or set to Low Gain mode. Output Parameters Enable: Click inside the box to turn the TRF6900 on or off. TXData: Click inside the box to switch the TXData line between high or low.
The chip layout screen can be accessed by double clicking on the left mouse button in the Help section of the main program screen. The chip layout screen appears as a simplified internal schematic of the TRF6900 as shown in Figure 3–2: Figure 3–2.
PLL/Modulation Options Screen The user can select FSK Modulation. The FSK Test button, located on the chip layout screen, will allow the user to transmit data using the TRF6900. Options for use with the FSK Test button are the pulse repetition frequency (PRF), which is defaulted to 100 Hz, and the Run Time (Min), which can be set in minutes.
TX_Data Low (MHz) frequencies, and their difference (Delta Fout kHz), are calculated and displayed. Press the Send Bits button located on the PLL/Modulation Options screen to program the TRF6900. Press the Close button to return to the chip layout screen. 3.5 Testing of Transmitter...
Testing of Transmitter Step 2: Software Programming: For testing the TRF6900 transmitter section, set the main program screen and the chip layout screen as shown in Figure 3–5 and Figure 3–6: Figure 3–5. Main Program Screen Double Clicking Here With Left Mouse...
Testing of Transmitter Chip Layout Screen of TRF6900 Software for Transmitter Testing Figure 3–6. Chip Layout Screen Clicking Here Will Set Power Amp Attenuation (0 dB, 10 dB, 20 dB) or Turn the Power Amp Off After setup is complete, press the Send Words button on the chip layout screen or the Send Words Now (F12) button on the main program screen to send the programming words to the TRF6900.
Testing of Transmitter Step 3: Spectrum Analyzer Setup and Clock Offset Procedure Set-up the spectrum analyzer to observe the following: Figure 3–7. Spectrum Analyzer Clock Offset Procedure 1) Use the test setup of Figure 3–4 and transmitter software setup as shown in Figure 3–5.
With Mouse to Set FSK Frequency Select to Program the TRF6900 Set the DVx bits, as shown in Figure 3–11, by double clicking inside each DVx box to set the value to either a 1 or 0. For this example only DV6 is set to a 1.
Testing of Transmitter Figure 3–11. PLL/Modulation Options Screen DV6 Display Set to 1 Frequency 915 MHz Frequency 915.10 MHz FSK Deviation of 100 kHz Send Bits Button Press the Send Words button on the chip layout screen or the Send Words Now (F12) on the main program screen.
This is FSK modulation with f 1 equal to 915.0 MHz, f 2 equal to 915.10 MHz and 100 Hz data rate. The f 1 frequency is the 0 frequency. The f 2 frequency is the 1 frequency. Figure 3–13. Block Diagram for Testing of the TRF6900 EVM Transmitter Section With an External Pulse Generator...
Testing of Transmitter To use an external pulse generator to supply transmit data, set up the test bench as shown in Figure 3–13. Perform the FSK modulation output test as described in the previous sec- tion. In this new setup, an external pulse generator is providing the modu- lation.
Testing of the Receiver 3.6 Testing of the Receiver Figure 3–15. Test Setup for TRF6900 Receiver Testing 10 kHz Pulse External Modulation Input Generator Signal Generator Pulse Generator Output Waveform Power Supply Voltage = 8 V Power Supply Cable DB25M to DB25F...
When Word Bits are Displayed in Red, the Send Words Now (F12) Button Must Be Pressed for Changes to Be Updated Note: The receiver frequency of the TRF6900 is 915.000 MHz. The TRF6900 is us- ing a 10.7-MHz IF frequency. Therefore, the local oscillator (LO) is set to a frequency of 904.30 MHz.
(V ) that is proportional to the average demodulation dc level. Capacitor C25 is connected to terminal 29 of the TRF6900 ( S&H_CA terminal). During the Hold Mode, the data slicer stops integrating and uses the dc voltage level stored on capacitor C25 as the decision threshold between a logic 1 and logic 0 as measured on terminal 28 DATA_OUT .
Testing of the Receiver 3.6.4 Measured Receive Data The data plots in Figure 3–18 and Figure 3–19, show the measured receive data at the AMP_OUT and RXDATA test points for input signals at –50 dBm and –90 dBm, respectively. Figure 3–18. Measured Data With –50 dBm Input Signal at AMP_OUT and RXDATA Test Points AMP_OUT Test Point...
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