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TPMC632-20R
Tews Technologies TPMC632-20R Manuals
Manuals and User Guides for Tews Technologies TPMC632-20R. We have
1
Tews Technologies TPMC632-20R manual available for free PDF download: User Manual
Tews Technologies TPMC632-20R User Manual (49 pages)
Reconfigurable FPGA with 64 TTL I/O / 32 Differential I/O Lines
Brand:
Tews Technologies
| Category:
I/O Systems
| Size: 1 MB
Table of Contents
Table of Contents
4
1 Product Description
7
Figure 1-1 : Block Diagram
7
2 Technical Specification
8
Table 2-1 : Technical Specification
9
3 Handling and Operation Instruction
10
ESD Protection
10
Thermal Considerations
10
4 Functional Description
11
FPGA Block Diagram
11
Figure 4-1 : Fpga Block Diagram
11
Fpga
12
Table 4-1 : Tpmc632 Fpga Feature Overview
12
Table 4-2 : Fpga Bank Usage
12
Gigabit Transceiver (GTP)
13
Figure 4-2 : Gtp Block Diagram
13
Table 4-3 : Gtp Connections
13
Table 4-4 : Multi Gigabit Transceiver Reference Clocks
13
Configuration
14
Figure 4-3 : Configuration Source Selection
14
Figure 4-4 : Configuration Dip-Switch Settings
14
Selecting the Configuration Source
14
Board Configuration CPLD
15
Figure 4-5 : Jtag-Chain
15
Figure 4-6 : Configuration Dip-Switch Settings
15
Jtag
15
Programming Configuration Devices
16
Clocking
17
Figure 4-7 : Fpga Clock Sources
17
FPGA Clock Sources
17
Table 4-5 : Available Fpga Clocks
17
I/O Interface
18
Table 4-6 : Digital I/O Interface
21
Ddr3 Sdram
22
Memory
22
Table 4-7 : Ddr3 Sdram Interface
23
SPI-Flash
24
Table 4-8 : Fpga Spi-Flash Connections
24
Table 4-9 : Fpga General Purpose I/O
25
User GPIO
25
On Board Indicators
26
Thermal Management
26
Table 4-10: Board-Status and User Leds
26
5 Design Help
27
Example Design
27
6 Installation
28
Pull up Voltage
28
Figure 6-1 : Pull (Up) Voltage Jumper Setting
28
I/O Interface
29
TTL I/O Interface
29
Figure 6-2 : Ttl I/O Interface
29
Differential I/O Interface
30
Multipoint-LVDS Interface
30
Figure 6-3 : Differential I/O Interface
30
Figure 6-4 : M-Lvds I/O Interface
30
Back I/O Configuration
31
Figure 6-5 : Jumper Positions for Ground Option
31
Figure 6-6 : Jumper Positions for Back I/O Options
32
FPGA Debug Connector
33
Connecting TA900 to TPMC632 Debug Connector
33
Figure 6-7 : Debug Connector X3
33
FPGA JTAG Connector
34
Figure 6-8 : Fpga Jtag Connector X2
34
7 Pin Assignment - I/O Connector
35
Overview
35
X1 Front Panel I/O Connector
35
Connector Type
35
Figure 7-1 : Front Panel I/O Connector Numbering
35
Pin Assignment
36
Table 7-1 : Pin Assignment Front Panel I/O Connector X1
36
Back I/O PMC Connector P14
37
Connector Type
37
Pin Assignment
37
Table 7-2 : Pin Assignment Back I/O Pmc Connector P14
38
X2 JTAG Header
39
Connector Type
39
Pin Assignment
39
Table 7-3 : Pin Assignment Jtag Header X2
39
X3 Debug-Connector
40
Connector Type
40
Pin Assignment
40
Table 7-4 : Pin Assignment Debug Connector X3
40
8 Known Issues
41
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