Renesas mPD703017A Manuals

Manuals and User Guides for Renesas mPD703017A. We have 1 Renesas mPD703017A manual available for free PDF download: User Manual

Renesas mPD703017A User Manual (494 pages)

32-Bit Single-chip Microcontroller

Brand: Renesas | Category: Microcontrollers | Size: 2 MB

Table of Contents
13
Chapter 1 Introduction

29
- General
  29
- Features
  30
- Applications
  32
- Ordering Information
  32
- Pin Configuration
  33
- Function Blocks
  36
- Internal Block Diagram
  36
- Internal Units
  37
Chapter 2 Pin Functions

40
Chapter 3 Cpu Functions

61
- Features
  61
- CPU Register Set
  62
- Program Register Set
  63
- System Register Set
  64
- Operation Modes
  67
- Address Space
  68
- CPU Address Space
  68
- Image
  69
- Image on Address Space
  69
- Wraparound of CPU Address Space
  70
- Program Space
  70
- Data Space
  70
- Memory Map
  71
- Area
  72
- Internal ROM Area (64 KB)
  72
- Internal ROM Area (128 KB)
  72
- Internal Rom/Internal Flash Memory Area (256 KB)
  73
- Internal RAM Area (4 KB)
  75
- Internal RAM Area (8 KB)
  75
- On-Chip Peripheral I/O Area
  76
- External Memory Area (When Expanded to 64 KB, 256 KB, or 1 MB)
  77
- External Memory Area (When Expanded to 4 MB)
  78
- External Expansion Mode
  79
- Recommended Use of Address Space
  81
- Application Example of Wraparound
  81
- Recommended Memory Map
  82
- Peripheral I/O Registers
  83
- Specific Registers
  88
Chapter 4 Bus Control Function

91
- Features
  91
- Bus Control Pins and Control Register
  91
- Bus Control Pins
  91
- Control Register
  92
- Bus Access
  92
- Number of Access Clocks
  92
- Bus Width
  93
- Byte Access (8 Bits)
  93
- Halfword Access (16 Bits)
  93
- Word Access (32 Bits)
  93
- Memory Block Function
  94
- Memory Space
  94
- Wait Function
  95
- Programmable Wait Function
  95
- External Wait Function
  96
- Relationship between Programmable Wait and External Wait
  96
- Wait Control
  96
- Example of Inserting Wait States
  96
- Idle State Insertion Function
  97
- Bus Hold Function
  98
- Outline of Function
  98
- Bus Hold Procedure
  99
- Operation in Power Save Mode
  99
- Bus Timing
  100
- Memory Read
  100
- Memory Write
  104
- Bus Hold Timing
  106
- Bus Priority
  107
- Memory Boundary Operation Conditions
  107
- Program Space
  107
- Data Space
  107
Chapter 5 Interrupt/Exception Processing Function

108
- Outline
  108
- Features
  108
- Non-Maskable Interrupts
  111
- Operation
  112
- Non-Maskable Interrupt Servicing
  112
- Acknowledging Non-Maskable Interrupt Request
  113
- Restore
  114
- RETI Instruction Processing
  114
- NP Flag
  115
- Noise Elimination of External Interrupt Request Input Pin
  115
- NP Flag (NP)
  115
- Edge Detection Function of External Interrupt Request Input Pin
  116
- Maskable Interrupts
  117
- Operation
  117
- Maskable Interrupt Servicing
  118
- Restore
  119
- RETI Instruction Processing
  119
- Priorities of Maskable Interrupts
  120
- Example of Multiple Interrupt Servicing
  121
- Example of Servicing Interrupt Requests Generated Simultaneously
  123
- Interrupt Control Register (Xxicn)
  124
- In-Service Priority Register (ISPR)
  127
- ID Flag
  128
- Watchdog Timer Mode Register (WDTM)
  128
- Interrupt Disable Flag (ID)
  128
- Software Exceptions
  129
- Operation
  129
- Software Exception Processing
  129
- Restore
  130
- RETI Instruction Processing
  130
- EP Flag
  131
- Exception Trap
  131
- Illegal Opcode Definition
  131
- EP Flag (EP)
  131
- Illegal Opcode
  131
- Operation
  132
- Exception Trap Processing
  132
- Restore
  133
- RETI Instruction Processing
  133
- Priority Control
  134
- Priorities of Interrupts and Exceptions
  134
- Multiple Interrupts
  134
- Interrupt Latency Time
  137
- Periods in Which Interrupts Are Not Acknowledged
  137
- Pipeline Operation at Interrupt Request Acknowledgement
  137
- Interrupt Request Valid Timing after EI Instruction
  138
- Interrupt Control Register Bit Manipulation Instructions During DMA Transfer
  139
- Pipeline Flow and Interrupt Request Signal Generation Timing
  139
Chapter 6 Clock Generation Function

140
- General
  140
- Configuration
  141
- Clock Output Function
  141
- Clock Generator
  141
- Control Registers
  142
- Power Save Functions
  145
- General
  145
- HALT Mode
  146
- IDLE Mode
  149
- Software STOP Mode
  150
- Oscillation Stabilization Time
  152
- Cautions on Power Save Function
  153
Chapter 7 Timer/Counter Function

155
Chapter 8 Watch Timer

210
- Functions
  210
- Block Diagram of Watch Timer
  210
- Configuration
  211
- Watch Timer Control Register
  212
- Operation
  213
- Operation as Watch Timer
  213
- Operation as Interval Timer
  213
- Cautions
  214
- Operation Timing of Watch Timer/Interval Timer
  214
- Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 S)
  214
Chapter 9 Watchdog Timer

215
- Functions
  215
- Block Diagram of Watchdog Timer
  215
- Configuration
  217
- Watchdog Timer Control Register
  217
- Operation
  220
- Operating as Watchdog Timer
  220
- Operating as Interval Timer
  221
- Standby Function Control Register
  222
Chapter 10 Serial Interface Function

223
- Overview
  223
- 3-Wire Serial I/O (CSI0 to CSI2)
  223
- Configuration
  224
- Block Diagram of 3-Wire Serial I/O
  224
- Csin Control Registers
  225
- Operations
  227
- Settings of Csimn (Operation Stop Mode)
  227
- Settings of Csimn (3-Wire Serial I/O Mode)
  228
- Timing of 3-Wire Serial I/O Mode
  229
- I C Bus (Interface I C)
  230
- Block Diagram of I 2 C
  231
- C Bus
  232
- Configuration
  233
- C Control Registers
  235
- I C Bus Mode Functions
  245
- Pin Configuration Diagram
  245
- C Bus Definitions and Control Methods
  246
- I 2 C Bus's Serial Data Transfer Timing
  246
- Start Condition
  246
- Address
  247
- Transfer Direction Specification
  248
- ACK Signal
  249
- Stop Condition
  250
- Wait Signal
  251
- C Interrupt Request (INTIIC0)
  253
- Interrupt Request (INTIIC0) Generation Timing and Wait Control
  271
- Address Match Detection Method
  272
- Error Detection
  272
- Extension Code
  272
- Arbitration
  273
- Arbitration Timing Example
  273
- Wakeup Function
  274
- Communication Reservation
  275
- Communication Reservation Timing
  276
- Timing for Acknowledging Communication Reservations
  276
- Communication Reservation Flow Chart
  277
- Cautions
  278
- Communication Operations
  279
- Master Operation Flow Chart
  279
- Slave Operation Flow Chart
  280
- Timing of Data Communication
  281
- Example of Master to Slave Communication (When 9-Clock Wait Is Selected for both Master and Slave)
  282
- Asynchronous Serial Interface (UART0, UART1)
  288
- Configuration
  288
- Uartn Control Registers
  290
- Operations
  296
- Standby Function
  309
Chapter 11 A/D Converter

310
- Function
  310
- Configuration
  312
- Control Registers
  314
- Operation
  318
- Basic Operation
  318
- Input Voltage and Conversion Result
  320
- A/D Converter Operation Mode
  321
- Notes on Using A/D Converter
  324
- How to Read A/D Converter Characteristics Table
  328
Chapter 12 Dma Functions

332
- Functions
  332
- Features
  332
- Configuration
  333
- Control Registers
  334
- Operation
  340
- Cautions
  341
Chapter 13 Real-Time Output Function (Rto)

342
- Function
  342
- Features
  342
- Configuration
  343
- Control Registers
  345
- Usage
  347
- Operation
  348
- Cautions
  349
Chapter 14 Port Function

350
- Port Configuration
  350
- Port Pin Function
  350
- Port 0
  350
- Port 1
  355
- Port 2
  361
- Port 3
  369
- Ports 4 and 5
  374
- Port 6
  377
- Ports 7 and 8
  379
- Port 9
  381
- Port 10
  385
- Port 11
  389
- Port 12
  392
- Setting When Port Pin Is Used as Alternate Function
  395
- Operation of Port Function
  398
- Writing Data to I/O Port
  398
- Reading Data from I/O Port
  398
Chapter 15 Reset Function

399
- General
  399
- Pin Operations
  399
Chapter 16 Flash Memory

400
- Features
  400
- Erasing Unit
  400
- Writing by Flash Programmer
  401
- Programming Environment
  406
- Communication System
  406
- Pin Connection
  409
- VPP Pin
  409
- Serial Interface Pin
  409
- RESET Pin
  411
- Port Pin (Including NMI)
  411
- Other Signal Pins
  411
- Power Supply
  411
- Programming Method
  412
- Flash Memory Control
  412
- Flash Memory Programming Mode
  412
- Selection of Communication Mode
  413
- Communication Command
  413
- Resources Used
  414
- Flash Memory Programming by Self-Programming
  415
- Outline of Self-Programming
  415
- Self-Programming Function
  416
- Outline of Self-Programming Interface
  417
- Hardware Environment
  417
- Software Environment
  419
- Self-Programming Function Number
  420
- Calling Parameters
  421
- Contents of RAM Parameters
  422
- Errors During Self-Programming
  423
- Flash Information
  423
- Area Number
  424
- Flash Programming Mode Control Register (FLPMC)
  425
- Calling Device Internal Processing
  427
- Flow of Erasing Flash Memory
  430
- Successive Writing Flow
  431
- Internal Verify Flow
  432
- Flow of Acquiring Flash Information
  433
- Self-Programming Library
  434
Chapter 17 Electrical Specifications

436
Chapter 18 Package Drawings

462
Chapter 19 Recommended Soldering Conditions

464
Appendix A Notes on Target System Design

468
Appendix B Register Index

470
Appendix C List of Instruction Sets

475
Appendix D Index

482
Appendix E Revision History

488

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Renesas mPD703017A Manuals

Renesas mPD703017A User Manual (494 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Functions

Chapter 4 Bus Control Function

Chapter 5 Interrupt/Exception Processing Function

Chapter 6 Clock Generation Function

Chapter 7 Timer/Counter Function

Chapter 8 Watch Timer

Chapter 9 Watchdog Timer

Chapter 10 Serial Interface Function

Chapter 11 A/D Converter

Chapter 12 Dma Functions

Chapter 13 Real-Time Output Function (Rto)

Chapter 14 Port Function

Chapter 15 Reset Function

Chapter 16 Flash Memory

Chapter 17 Electrical Specifications

Chapter 18 Package Drawings

Chapter 19 Recommended Soldering Conditions

Appendix A Notes on Target System Design

Appendix B Register Index

Appendix C List of Instruction Sets

Appendix D Index

Appendix E Revision History

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