Freescale Semiconductor PXR4030 Reference Manual

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PXR40 Microcontroller

Reference Manual

Devices Supported:

PXR4030

PXR4040

PXR40RM

Rev. 1

06/2011

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Page 1 PXR40 Microcontroller Reference Manual Devices Supported: PXR4030 PXR4040 PXR40RM Rev. 1 06/2011...
Page 2 Freescale Semiconductor China Ltd. application in which the failure of the Freescale Semiconductor product could Exchange Building 23F create a situation where personal injury or death may occur. Should Buyer No.
Page 3: Table Of Contents
3.3.9 EBI Signals ..................3-50 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 4 5.5.8 Trimming ..................5-20 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 5 7.3.1.4 External Interrupt Status Register (SIU_EISR) ............7-15 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 6 Functional Description ..................9-3 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 7 10.5.8 Lowering Priority Within an ISR ..............10-43 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 8 13.1 Overview ................... . . 13-1 PXR40 Microcontroller Reference Manual, Rev. 1 viii Freescale Semiconductor...
Page 9 14.2.1 Register Descriptions ................14-4 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 10 17.1.1 Features ..................17-1 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 11 19.4 Functional Description ................. . . 19-6 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 12 21.5.1 eDMA Initialization ................21-44 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 13 22.5.2.17 Channel A Status Error Counter Register (CASERCR) ..........22-30 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor xiii...
Page 14 22.6.3.3 Receive FIFO ................22-79 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 15 22.6.18Slot Status Monitoring ................22-140 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 16 23.6 Interrupts ................... . 23-65 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 17 24.5.2 FlexCAN Addressing and RAM size configurations ............24-49 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor xvii...
Page 18 25.4.4.3 DSI Serialization ................25-39 PXR40 Microcontroller Reference Manual, Rev. 1 xviii Freescale Semiconductor...
Page 19 26.3.2.1 Baud Rate Register (eSCI_BRR) ..............26-8 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 20 27.6.2 EQADC Register Descriptions ..............27-16 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 21 27.8.3 Sending Immediate Command Setup Example ............27-122 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 22 28.3.15Enhanced Debug Monitor Description ..............28-43 PXR40 Microcontroller Reference Manual, Rev. 1 xxii Freescale Semiconductor...
Page 23 29.3.2.1 System Configuration ............... . 29-48 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor xxiii...
Page 24 30.2.3.9 D_TEA — Transfer Error Acknowledge ............30-7 PXR40 Microcontroller Reference Manual, Rev. 1 xxiv Freescale Semiconductor...
Page 25 31.2 External Signal Description ................31-5 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 26 31.13.2BTM Message Formats ................31-42 PXR40 Microcontroller Reference Manual, Rev. 1 xxvi Freescale Semiconductor...
Page 27 31.17.5.1 Data Trace ................31-79 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor xxvii...
Page 28 33.3.4 Crossbar Switch ................. . 33-5 PXR40 Microcontroller Reference Manual, Rev. 1 xxviii Freescale Semiconductor...
Page 29 34.3.6.2 Temperature Calculation Constants Register 1 ........... . . 34-5 Appendix A Revision History of this Document PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor xxix...
Page 30: Pxr40 Microcontroller Reference Manual,
PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 31: Introduction
Chapter 5, Power Management Controller (PMC), describes the on-chip module that provides voltage regulation for the PXR40. • Chapter 6, Frequency Modulated Phase-Locked Loop (FMPLL), describes the features and function of the FMPLL module. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor xxxi...
Page 32 I/O channels for communications with off-chip devices. • Chapter 24, FlexCAN Module, describes the FlexCAN module, a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B and ISO Standard 11898. PXR40 Microcontroller Reference Manual, Rev. 1 xxxii Freescale Semiconductor...
Page 33 Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield • Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David A. Patterson. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor xxxiii...
Page 34 (Chapter 1) of a device’s reference manual. • Application notes—These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors. Additional literature is published as new processors become available. For a current list of PowerPC documentation, refer to http://www.freescale.com/powerpc.
Page 35 The only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless of length. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor xxxv...
Page 36 Institute for Electrical and Electronics Engineers Instruction fetch pipeline Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, first-out Least recently used Least-significant byte Least-significant bit PXR40 Microcontroller Reference Manual, Rev. 1 xxxvi Freescale Semiconductor...
Page 37 Universal asynchronous/synchronous receiver transmitter Universal serial bus Terminology conventions Table ii shows terminology conventions used throughout this document. Table ii. Notational Conventions Instruction Operand Syntax Opcode Wildcard Logical condition (example: NE for not equal) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor xxxvii...
Page 38 Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) Operations Arithmetic addition or postincrement indicator – Arithmetic subtraction or predecrement indicator Arithmetic multiplication PXR40 Microcontroller Reference Manual, Rev. 1 xxxviii Freescale Semiconductor...
Page 39 Calculated effective address (pointer) Bit selection (example: Bit 3 of D0) Least significant bit (example: lsb of D0) Least significant byte Least significant word Most significant bit Most significant byte Most significant word PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor xxxix...
Page 40 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 41: Pxr40 Features
(first 1 MB of memory is 4 × 128; last 3 MB are 4 × 256) External bus Calibration bus 16 bit non-muxed 32 bit muxed 96 channel DMA Nexus Class 3 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 42 Yes (8 on eQADC_B) Sensor diagnostics Supplies Low Power Modes Stop Mode Slow Mode Note: 3.3 V is required for certain IO segments only during debug/development (e.g., Nexus 3 trace and bus) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 43: Block Diagram
– Enhanced modular I/O system local interconnect network eQADC – Enhanced queued A/D converter module – Variable length instruction encoding eTPU2 – Enhanced time processing unit 2 Figure 1-1. PXR40 block diagram PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 44: Critical Performance Parameters
— Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation • 256 KB on-chip general-purpose SRAM including 32 KB of standby RAM • Two direct memory access controller (eDMA2) blocks — One supporting 64 channels PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 45: Module Features
The following sections provide more details of the modules implemented on the PXR40. 1.2.3 High-performance e200z7 core processor The e200z7 core includes the following features: ® • Dual-issue, 32-bit Power Architecture • Supports the 32-bit Power Architecture Book E programmer’s model PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 46: On-Chip Flash Memory
— Configurable read buffering and line prefetch support • An interface between the system bus and a dedicated flash memory array controller PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 47: General-Purpose Static Ram (Sram)
— Single-bit correction reporting for SRAM and flash memory — Multi-bit error reporting • Includes facilities to allow CPU software to test the error ECC and EDC operation for on-chip memories by supporting injection of arbitrary error patterns PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 48: Enhanced Modular Input Output System (Timer-Emios)
32 standard channels, each channel is associated with one input and one output signal • Two independent 24-bit time bases for channel synchronization: • Event-triggered microengine — 24 KB of code memory (SCM) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 49: Software Watchdog Timer (Swt)
Programmable selection of reset or interrupt on an initial time-out • Master access protection • Hard and soft configuration lock bits • Reset configuration inputs allow timer to be enabled out of reset PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 50: Periodic Interrupt Timer (Pit)
FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band noise, while providing a reduced sample PXR40 Microcontroller Reference Manual, Rev. 1 1-10 Freescale Semiconductor...
Page 51 — Free-running clock for use by an external device — Supports a 26-bit message length • Six priority-based queues per ADC • Trigger sources include software, timer channels and input pins PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 1-11...
Page 52: Serial Peripheral Interface Module (Spi)
For queued operations, the SPI queues reside in system memory external to the SPI. Data transfers between the memory and the SPI FIFOs are accomplished through the use of the eDMA2 controller or through host software. PXR40 Microcontroller Reference Manual, Rev. 1 1-12 Freescale Semiconductor...
Page 53: Serial Communication Interface Module (Uart)
– Autonomous LIN response handling – Discarding of irrelevant LIN responses using up to 16 ID filters 1.2.15 Controller area network (CAN) module The PXR40 contains four controller area network (CAN) blocks. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 1-13...
Page 54: Enhanced Direct Memory Access Controller (Edma2)
The following summarizes the PXR40’s implementation of the eDMA2 controller: • Second-generation modules capable of performing complex data movements via 64 programmable channels (eDMA2-A) and 32 programmable channels (eDMA2-B), without intervention from the host processor • DMA engine PXR40 Microcontroller Reference Manual, Rev. 1 1-14 Freescale Semiconductor...
Page 55: Crossbar Switch (Xbar)
— eDMA2 module A — eDMA2 module B — FlexRay — Nexus debug interface (NDI) • Four slave ports — Flash memory — SRAM — Peripheral bridge A — Peripheral bridge B PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 1-15...
Page 56: Power Management Unit (Pmu)
Support for a critical or non maskable interrupt — Non-maskable interrupt (NMI) multiplexed on WKPCFG pin to allow connection to the critical or non maskable input of the CPU core, bypassing the interrupt controller and all PXR40 Microcontroller Reference Manual, Rev. 1 1-16 Freescale Semiconductor...
Page 57: Frequency-Modulated Pll (Fmpll)
Configuration registers defined as an upwardly compatible superset of MPC5500 FMPLL registers 1. You must configure the FMPLL to ensure that the maximum specified system frequency is not exceeded when frequency modulation is enabled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 1-17...
Page 58: System Integration Unit (Siu)
PXR40 hardware accordingly. The BAM provides the following features: • Sets up MMU to cover all resources and mapping all physical addresses to logical addresses with minimum address translation PXR40 Microcontroller Reference Manual, Rev. 1 1-18 Freescale Semiconductor...
Page 59: Dual-Channel Flexray Controller
— Each segment can contain message buffers assigned to the static segment and message buffers assigned to the dynamic segment at the same time 1. Feature available only on revision 2 release of device. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 1-19...
Page 60: Jtag Controller (Jtagc)
IEEE 1149.1-2001 Test Access Port (TAP) interface five pins (JCOMP, TDI, TMS, TCK, and TDO) • IEEE 1149.7 Serial JTAG Test Access Port interface three pins (JCOMP, TMS, TCK) • A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: PXR40 Microcontroller Reference Manual, Rev. 1 1-20 Freescale Semiconductor...
Page 61: Nexus
— One EVTO (event out) pin – Auxiliary input port — One EVTI (event in) pin — 5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK) or 3-pin (JCOMP, TMS, and TCK) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 1-21...
Page 62: Developer Environment
The PXR40 supports several tools to enable easier application development. The following development support will be available. • Tower system modules for evaluation and prototyping • Compilers • Debuggers • JTAG and Nexus interfaces • RAppID™ Initialization tool PXR40 Microcontroller Reference Manual, Rev. 1 1-22 Freescale Semiconductor...
Page 63: Memory Map
Internal SRAM (224 KB) 0x4000_8000—0x4003_FFFF Reserved 0x4004_0000—0xC3EF_FFFF Peripheral Bridge A Registers 0xC3F0_0000—0xC3F0_3FFF Reserved 0xC3F0_4000—0xC3F7_FFFF FMPLL 0xC3F8_0000—0xC3F8_3FFF EBI Configuration 0xC3F8_4000—0xC3F8_7FFF Flash A Configuration 0xC3F8_8000—0xC3F8_BFFF Flash B Configuration 0xC3F8_C000—0xC3F8_FFFF 0xC3F9_0000—0xC3F9_3FFF Reserved 0xC3F9_4000—0xC3F9_FFFF eMIOS 0xC3FA_0000—0xC3FA_3FFF Reserved 0xC3FA_4000—0xC3FB_BFFF PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 64 0xFFF8_0000—0xFFF8_3FFF eQADC_B 0xFFF8_4000—0xFFF8_7FFF Decimation filter A 0xFFF8_8000—0xFFF8_87FF Decimation filter B 0xFFF8_8800—0xFFF8_8FFF Decimation filter C 0xFFF8_9000—0xFFF8_97FF Decimation filter D 0xFFF8_9800—0xFFF8_9FFF Decimation filter E 0xFFF8_A000—0xFFF8_A7FF Decimation filter F 0xFFF8_A800—0xFFF8_AFFF Decimation filter G 0xFFF8_B000—0xFFF8_B7FF PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 65 0xFFFB_C0000—0xFFFB_FFFF FlexCAN_A 0xFFFC_0000—0xFFFC_3FFF FlexCAN_B 0xFFFC_4000—0xFFFC_7FFF FlexCAN_C 0xFFFC_8000—0xFFFC_BFFF FlexCAN_D 0xFFFC_C000—0xFFFC_FFFF Reserved 0xFFFD_0000—0xFFFD_FFFF FlexRay 0xFFFE_0000—0xFFFE_3FFF Reserved 0xFFFE_4000—0xFFFE_BFFF System Information Module (temp. sensor 0xFFFE_C000—0xFFFE_FFFF and unique device ID) Reserved 0xFFFF_0000—0xFFFF_BFFF Boot Assist Module (BAM) 0xFFFF_C000—0xFFFF_FFFF PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 66 Memory Map PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 67: Signal Descriptions
PA is set to a value that deselects its LVDS signal. The ball that has its PA field still set to LVDS will go to an undriven state until its PA field is updated to a non-LVDS value. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 68 Table 3-3. Differential Signal Output when LVDS is Enabled Current Differential Voltage Across SRC1 SRC0 flowing in the ‘true’ and ‘complement’ driver normal default increased increased (20%) decreased decreased (20%) normal same as default PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 69: External Signal Descriptions, Pin Multiplexing, And Attributes
External Signal Descriptions, Pin Multiplexing, and Attributes This section summarizes the external signal functions, their static electrical characteristics, and pad configuration settings for this device. The signal properties and their electrical characteristics are set in the System Integration Unit (SIU) Pad Configuration (PCR) registers.
Page 70 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 117 ETPUA3_ETPUA15_ ETPUA3 eTPU A channel —/WKPCFG —/WKPCFG DDEH1 GPIO117 ETPUA15 eTPU A channel (output only) — — —...
Page 71 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 123 ETPUA9_ETPUA21_ ETPUA9 eTPU A channel —/WKPCFG —/WKPCFG DDEH1 GPIO123 ETPUA21 eTPU A channel (output only) — — —...
Page 72 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 129 ETPUA15_PCSB5_ ETPUA15 eTPU A channel —/WKPCFG —/WKPCFG DDEH1 GPIO129 PCSB5 DSPI B peripheral chip select — — —...
Page 73 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 135 ETPUA21_IRQ9_ ETPUA21 eTPU A channel —/WKPCFG —/WKPCFG DDEH1 GPIO135 IRQ9 External interrupt request — — — GPIO135 GPIO 136 ETPUA22_IRQ10_ ETPUA22...
Page 74 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 141 ETPUA27_IRQ15_ ETPUA27 eTPU A channel —/WKPCFG —/WKPCFG DDEH1 GPIO141 IRQ15 External interrupt request — — — GPIO141 GPIO 142 ETPUA28_PCSC1_ ETPUA28...
Page 75 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 147 ETPUB0_ETPUB16_ ETPUB0 eTPU B channel —/WKPCFG —/WKPCFG DDEH6 GPIO147 ETPUB16 eTPU B channel (output only) — — —...
Page 76 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 153 ETPUB6_ETPUB22_ ETPUB6 eTPU B channel —/WKPCFG —/WKPCFG DDEH6 GPIO153 ETPUB22 eTPU B channel (output only) — — —...
Page 77 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 159 ETPUB12_ETPUB28_ ETPUB12 eTPU B channel —/WKPCFG —/WKPCFG DDEH6 GPIO159 ETPUB28 eTPU B channel (output only) — — —...
Page 78 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 165 ETPUB18_PCSA3_ ETPUB18 eTPU B channel —/WKPCFG —/WKPCFG DDEH6 GPIO165 PCSA3 DSPI A peripheral chip select — — —...
Page 79 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 171 ETPUB24_ ETPUB24 eTPU B channel —/WKPCFG —/WKPCFG DDEH6 GPIO171 — — — — — — GPIO171 GPIO 172 ETPUB25_ ETPUB25 eTPU B channel...
Page 80 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 177 ETPUB30_ ETPUB30 eTPU B channel —/WKPCFG —/WKPCFG AA24 DDEH6 GPIO177 — — — — — — GPIO177 GPIO 178 ETPUB31_ ETPUB31...
Page 81 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 444 ETPUC3_ — — — —/WKPCFG —/WKPCFG DDEH7 GPIO444 — — — — — — GPIO444 GPIO 445 ETPUC4_ —...
Page 82 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 450 ETPUC9_IRQ0_ — — — —/WKPCFG —/WKPCFG DDEH7 GPIO450 IRQ0 External interrupt request — — — GPIO450 GPIO 451 ETPUC10__IRQ1_ —...
Page 83 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 456 ETPUC15__ — — — —/WKPCFG —/WKPCFG DDEH7 GPIO456 — — — — — — GPIO456 GPIO 457 ETPUC16_FR_A_TX_ —...
Page 84 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 462 ETPUC21_TXDB_ — — — —/WKPCFG —/WKPCFG DDEH7 GPIO462 TXDB eSCI B transmit — — — GPIO462 GPIO 463 ETPUC22_RXDB_ —...
Page 85 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 467 ETPUC26_PCSD2_ — — — —/WKPCFG —/WKPCFG DDEH7 GPIO467 PCSD2 DSPI D peripheral chip select — — — GPIO467 GPIO 468 ETPUC27_PCSD1_...
Page 86 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 179 EMIOS0_ETPUA0_ EMIOS0 eMIOS channel —/WKPCFG —/WKPCFG AE10 DDEH4 GPIO179 ETPUA0 eTPU A channel — — — GPIO179 GPIO 180 EMIOS1_ETPUA1_ EMIOS1...
Page 87 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 185 EMIOS6_ETPUA6_ EMIOS6 eMIOS channel —/WKPCFG —/WKPCFG AE12 DDEH4 GPIO185 ETPUA6 eTPU A channel — — — GPIO185 GPIO 186 EMIOS7_ETPUA7_ EMIOS7...
Page 88 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 191 EMIOS12_SOUTC_ EMIOS12 eMIOS channel —/WKPCFG —/WKPCFG AF14 DDEH4 GPIO191 SOUTC DSPI C data output — — — GPIO191 GPIO 192 EMIOS13_SOUTD_...
Page 89 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 197 EMIOS18_ETPUB2_ EMIOS18 eMIOS channel —/WKPCFG —/WKPCFG AC15 DDEH4 GPIO197 ETPUB2 eTPU B channel FR_DBG[1] FlexRay debug GPIO197 GPIO 198 EMIOS19_ETPUB3_ EMIOS19...
Page 90 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 203 EMIOS24_PCSB0_ EMIOS24 eMIOS channel —/WKPCFG —/WKPCFG AF17 DDEH4 GPIO203 PCSB0 DSPI B peripheral chip select — — —...
Page 91 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 436 EMIOS30_PCSC2_ EMIOS30 eMIOS channel —/WKPCFG —/WKPCFG AD18 DDEH4 GPIO436 PCSC2 DSPI C peripheral chip select — — —...
Page 92 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) — ANA11 ANA11 eQADC A analog input ANA11 ANA11 DDA_A1 — ANA12 ANA12 eQADC A analog input ANA12 ANA12 DDA_A1 —...
Page 93 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) — AN36 AN36 eQADC A and B shared analog input AN36 AN36 DDA_B1 — AN37 AN37 eQADC A and B shared analog input AN37 AN37 DDA_B0...
Page 94 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) — ANB16 ANB16 eQADC B analog input ANB16 ANB16 DDA_B0 — ANB17 ANB17 eQADC B analog input ANB17 ANB17 DDA_B0 —...
Page 95 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) FlexRay 248 FR_A_TX_ FR_A_TX FlexRay A transfer —/Up —/Up DDE2 GPIO248 (–/– for Rev.1 (–/– for Rev.1 — —...
Page 96 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) FlexCAN CNTXA_TXDA_ CNTXA FlexCAN A transmit —/Up —/Up AF19 DDEH4 GPIO83 TXDA eSCI A transmit — — — GPIO83 GPIO CNRXA_RXDA_...
Page 97 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 246 CNTXD_ CNTXD FlexCAN D transmit —/Up —/Up AD20 DDEH4 GPIO246 — — — — — — GPIO246 GPIO 247 CNRXD_ CNRXD...
Page 98 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 244 TXDC_ETRIG0_ TXDC eSCI C transmit —/Up —/Up AF23 DDEH4 GPIO244 ETRIG0 eQADC trigger input — — — GPIO244 GPIO 245 RXDC_...
Page 99 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) PCSA1_ PCSA1 DSPI A peripheral chip select —/Up —/Up DDEH3 GPIO97 — — — — — — GPIO97 GPIO PCSA2_ PCSA2...
Page 100 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 103 SINB_ SINB DSPI B data input —/Up —/Up DDEH3 GPIO103 — — — — — — GPIO103 GPIO 104 SOUTB_ SOUTB...
Page 101 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 109 PCSB4_SCKC_ PCSB4 DSPI B peripheral chip select —/Up —/Up DDEH3 GPIO109 SCKC DSPI C clock — — —...
Page 102 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 238 PCSC0_SOUT_C_LVDSM_ PCSC0 DSPI C peripheral chip select —/Up —/Up AE21 DDEH4 GPIO238 LVDS SOUT_C_LVDSM LVDS– downstream signal negative output data —...
Page 103 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) Reset and Clocks — RESET RESET External reset input RESET/Up RESET/Up DDEH1 230 RSTOUT RSTOUT External reset output RSTOUT/Low RSTOUT/ DDEH1...
Page 104 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 214 ENGCLK ENGCLK EBI engineering clock output ENGCLK/ ENGCLK/ DDE2 Enabled Enabled Note: EXTCLK (External clock input) selected through SIU register) JTAG and Nexus (see footnote about resets)
Page 105 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) MDO4_GPIO75 – MDO4 Nexus message data out O/Low —/Down DDE2 (GPIO function on this pin is — — —...
Page 106 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) MDO10_GPIO81 – MDO10 Nexus message data out O/Low —/Down DDE2 (GPIO function on this pin is — — —...
Page 107 Table 3-4. Signal Properties and Muxing Summary (continued) State State Package Signal Name Function Function Summary during after Location RESET RESET (416) 225 MSEO1 – MSEO1 Nexus message start/end out O/Low MSEO/HI DDE2 226 RDY – Nexus ready output O/Low RDY/HI DDE2 —...
Page 108 MH = High voltage, medium speed F = Fast speed FS = Fast speed with slew AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad) VHV = Very high voltage VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments.
Page 109: Detailed Signal Description
ETPUB[0:15]_ETPUB[16:31]_GPIO[147:162] are 16 input/output channel pins for the GPIO[147:162] eTPU B module. The alternate functions are output channels for the eTPU B module; that is, when configured as ETPUB[16:31], the pins function as outputs only. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 3-43...
Page 110: Irq And Gpio Signals
This pin does not have a primary function assigned to it. The alternate function is an ETPUC14_ external interrupt request input for the SIU module. GPIO456 This pin does not have a primary function assigned to it. ETPUC15_ PXR40 Microcontroller Reference Manual, Rev. 1 3-44 Freescale Semiconductor...
Page 111: Emios Signals
Output channel pins for the eMIOS module. Alternate function peripheral chip select for the DSPI C module. EMIOS31_PCSC5_GPIO437 Output channel pins for the eMIOS module. Alternate function peripheral chip select for the DSPI C module. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 3-45...
Page 112: Eqadc Signals
FlexRay Channel A receive pin. FR_A_TX_EN_GPIO250 FlexRay Channel A transmit enable pin. FR_B_TX_GPIO251 FlexRay Channel B transmit pin. FR_B_RX_GPIO252 FlexRay Channel B receive pin. FR_B_TX_EN_GPIO253 FlexRay Channel B transmit enable pin. PXR40 Microcontroller Reference Manual, Rev. 1 3-46 Freescale Semiconductor...
Page 113: Flexcan Signals
Transmit data pin for the eSCI B module. The alternate function is a peripheral chip select output for the DSPI D module. RXDB_PCSD5_GPIO92 Receive pin for the eSCI B module. The alternate function is a peripheral chip select output for the DSPI D module. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 3-47...
Page 114: Dspi Signals
The eQADC external trigger input pins can be connected to the eTPU, the eMIOS, or an external signal. The source is selected by configuring the eQADC trigger source in the SIU_ISEL4-7 registers. ETRIG[1] serves as the external trigger for CFIFO1, CFIFO3, and CFIFO5. PXR40 Microcontroller Reference Manual, Rev. 1 3-48 Freescale Semiconductor...
Page 115 DSPI D module. PCSD0_GPIO469 This pin does not have a primary function assigned to it. The alternate function is a ETPUC28_ peripheral chip select for the DSPI D module. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 3-49...
Page 116: Ebi Signals
D_ADD14_GPIO261 D_ADD15_GPIO262 D_ADD16_D_DAT16_GPIO263 EBI address signals with alternate functions of EBI data signals. D_ADD17_D_DAT17_GPIO264 D_ADD18_D_DAT18_GPIO265 D_ADD19_D_DAT19_GPIO266 D_ADD20_D_DAT20_GPIO267 D_ADD21_D_DAT21_GPIO268 D_ADD22_D_DAT22_GPIO269 D_ADD23_D_DAT23_GPIO270 D_ADD24_D_DAT24_GPIO271 D_ADD25_D_DAT25_GPIO272 D_ADD26_D_DAT26_GPIO273 D_ADD27_D_DAT27_GPIO274 D_ADD28_D_DAT28_GPIO275 D_ADD29_D_DAT29_GPIO276 D_ADD30_D_DAT30_GPIO277 D_DAT[0:15]_GPIO[278:293] EBI data signals. PXR40 Microcontroller Reference Manual, Rev. 1 3-50 Freescale Semiconductor...
Page 117: Reset And Clock Signals
The alternate functions are an external interrupt request input and data output for the DSPI module D. PLLCFG2 PLLCFGn are sampled at every reset. These values are used to configure the FMPLL operation mode. PLLCFG2 configures the crystal oscillator range. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 3-51...
Page 118: Jtag And Nexus Signals
TEST places the chip into test mode. You must tie this pin to VSS. GPIO function for MDO[11:0] is only available on Rev.2 of the device. Do not connect pin directly to a power supply or ground. PXR40 Microcontroller Reference Manual, Rev. 1 3-52 Freescale Semiconductor...
Page 119: Pmc And Power/Voltage Signals
DDAn VDDA_B1 is the analog supply input pin for the eQADC_B. DDAn VSSA_B0 is the analog ground reference input pin for the eQADC_B. SSAn PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 3-53...
Page 120 Signal Descriptions PXR40 Microcontroller Reference Manual, Rev. 1 3-54 Freescale Semiconductor...
Page 121: Reset Sources
Table 4-1. BOOTCFG Options BOOTCFG[0] BOOTCFG[1] Meaning Boot from internal flash memory FlexCAN / eSCI boot Boot from external memory Boot from external memory This mode is only available in packages that have an EBI. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 122: Reset Vector
The RESET pin has a glitch detector which detects spikes greater than 2 clocks in duration that fall below the switch point of the input buffer logic of the VDDEH input 1. BOOTCFG[0] is not available on all packages. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 123: Rstout
For the following reset source descriptions refer to the reset flow diagrams in Figure 4-1 Figure 4-2. Figure 4-1 shows the reset flow for assertion of the RESET pin. Figure 4-2 shows the internal processing of reset for all reset sources. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 124 RESET Asserted? Wait 2 Clock Cycles RESET Asserted? Set Latch, Wait 8 Clock Cycles RESET Set RGF Bit Asserted? To entry point in internal reset flow Figure 4-1. External Reset Flow Diagram PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 125 Wait 24001 Clock Cycles Negate Internal Resets and RSTOUT NOTES: 1. The clock count is dependent on the configuration of the PLL (refer to Section 4.3.2, RSTOUT). Figure 4-2. Internal Reset Flow Diagram PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 126: Power-On Reset (Por)
(assertion of RSTOUT). Once the FMPLL Loss of Lock reset request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT). Once PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 127: Loss Of Clock
JTAG controller. The internal reset signal is asserted. The state of the RSTOUT pin is determined by the JTAG instruction. The values on the WKPCFG and PLLCFG pins are applied at the PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 128: Software System Reset
The System Integration Unit (SIU) on this device includes two registers, SIU_RSR and SIU_SRCR, that affect the reset behavior of this device. See Chapter 7, System Integration Unit (SIU),for descriptions of these registers. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 129: Reset Configuration
When booting from the external flash device, the RCHW must reside in the first 16 bits of memory. BOOT_BLOCK_ADDRESS + 0x0000_0000 SWT WTE Boot Identifier = 0x5A Figure 4-3. Reset Configuration Half Word PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 130 PLL is programmed with different multipliers. Table 4-6. Watchdog timeout periods Crystal Frequency (MHz) Core WD Timeout (ms) SWT Timeout (ms) 27.3 18.3 32.7 13.7 24.5 19.6 PXR40 Microcontroller Reference Manual, Rev. 1 4-10 Freescale Semiconductor...
Page 131: Reset Configuration Timing
If the WKPCFG signal is logic low at the assertion of the internal reset signal, pull down devices will be enabled on those pins. The value on WKPCFG must be held constant during reset to avoid oscillations on PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 4-11...
Page 132 The final value of WKPCFG is latched 4 clock cycles before the negation of RSTOUT. After reset, software may modify the weak pull up/down selection for all I/O pins through the PCR registers in the SIU. PXR40 Microcontroller Reference Manual, Rev. 1 4-12 Freescale Semiconductor...
Page 133: Power Management Controller (Pmc)
Its low accuracy requires that temperature is checked with the included precision temperature sensor before taking any corrective action. • Direct measurement of PMC internal voltages is available at predefined ADC channels. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 134: Analog Pmc_Smps Features
POR level of reset pin segement (VDDEH1) • low voltage detects for other IO segement LVD (VDDEH3, VDDEH4, VDDEH5, VDDEH6, VDDEH7) • low voltage detect on VDDA (from ADC band gap reference) • standby regulator brownout circuit PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 135: Block Diagram
3.3V regulator is disabled with tri-stated output. VDDSYN must be connected to VDDREG. An external ballast transistor is expected on REGCTL as described in 1.2V LDO regulator section. VDDREG LVD selected to 3V nominal. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 136: External Signals Description
Positive analog power supply for PMC and voltage regulators. It can be nominal 5V or nominal 3.3V. It supplies internal regulators and LVDs. Voltage range VDDR for 5V operation and VDD33 for 3V operation can be found in the PXR40 Microcontroller Data Sheet. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 137: Vdd
Sense point for LVD and regulator feedback of the 3.3V VDDSYN analog supply. Input that produces 3.3V regulator reference and LVD 3.3V reference. Must be shorted to VDDSYN with low impedance connection. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 138: Memory Map/Register Definition
0 Disabled. LVD assertion on the VDDREG supply of the voltage regulator does not cause system reset. 1 Enabled. LVD assertion on the VDDREG supply of the voltage regulator causes system reset. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 139 If both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 Disabled. Low-voltage interrupt request is disabled. 1 Enabled. Low-voltage interrupt request is enabled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 140: Trimming Register (Pmc_Trimr)
Offset: PMC_BASE + 0x0004 Access: User read/write LVDATRIM LVDREGTRIM Reset VDD33TRIM LVD33TRIM VDDCTRIM LVDCTRIM Reset Figure 5-3. Trimming Register (PMC_TRIMR) Table 5-5. PMC_TRIMR Field Descriptions Field Description 0–7 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 141 1101 LvdReg + 2 * LVDSTEPREG 1100 LvdReg + 3 * LVDSTEPREG 1011 LvdReg + 4 * LVDSTEPREG 1010 LvdReg + 5 * LVDSTEPREG 1001 LvdReg + 6 * LVDSTEPREG 1000 LvdReg + 7 * LVDSTEPREG PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 142 1111 Nominal, start-up and default value of LVD33 1101 LVD33+1 * LVDSTEP33 1110 LVD33+2 * LVDSTEP33 1100 LVD33+3 * LVDSTEP33 1011 LVD33+4 * LVDSTEP33 1001 LVD33+5 * LVDSTEP33 1010 LVD33+6 * LVDSTEP33 1000 LVD33+7 * LVDSTEP33 PXR40 Microcontroller Reference Manual, Rev. 1 5-10 Freescale Semiconductor...
Page 143 1100 Default LVD12 value to be programmed immediately after reset if core voltage internal regulator is used 1011 LVD12+ 1* LVDSTEP12 1001 LVD12+ 2* LVDSTEP12 1010 LVD12+ 3* LVDSTEP12 1000 LVD12+ 4* LVDSTEP12 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 5-11...
Page 144: Status Register (Pmc_Sr)
I/O segment that contains the reset pin. Writing 1 to this bit clears LVFR. Writing 0 has no effect. Reading this bit always returns 0. 0 No effect. 1 Clears LVFR. PXR40 Microcontroller Reference Manual, Rev. 1 5-12 Freescale Semiconductor...
Page 145 CPU. If LVRE50 is also asserted, a system reset will be generated, which will clear LVF50 and negate the interrupt request. 0 No occurrence. 1 LVD occurrence detected on the VDDREG supply of the voltage regulator. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 5-13...
Page 146: Functional Description
1.2V regulated voltage supply VDD. As both target regulated voltage VDD12OUT and LVD level LVD12 rely on bandgap voltage, an equivalent variation is to be PXR40 Microcontroller Reference Manual, Rev. 1 5-14 Freescale Semiconductor...
Page 147: Pmc Internal 1.2V Voltage Regulator Selection
SOC from external source; whereas in the LDO5V mode, VDDSYN is connected back to VDD33. When the LDO regulator is selected in LDO3V or LDO5V mode both nominal 5.0 V and 3.3 V are allowed. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 5-15...
Page 148: Pmc Bandgap
In this case it is recommended that the supplied 3.3V is nominal 3.5V +/- 3% during start up when both regulators may be enabled. For the correct operation of the device the externally supplied VDD33 voltage must be higher than the maximum correspondent LVD rising voltage LVD33. PXR40 Microcontroller Reference Manual, Rev. 1 5-16 Freescale Semiconductor...
Page 149: 3.3V Vddsyn Lvd
“1111”. 5.5.5 3.3V VDDSYN LVD A user programmable low voltage detector (LVD) monitors the voltage VDDSYN. Rising LVD threshold voltage is documented under LVD33 symbol in the PXR40 Microcontroller Data Sheet. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 5-17...
Page 150: Voltage Regulator Controller
In case of NPN device a minimum beta of 50, maximum current rating >1.5A; • In case of high side driver maximum threshold voltage of 1.5V, gate capacitance less than 5nF, maximum current rating >2A. PXR40 Microcontroller Reference Manual, Rev. 1 5-18 Freescale Semiconductor...
Page 151: 1.2V Vdd Lvd
LVD scaled voltage can be measured via ADC by selecting the respective channel reported in Table 5-8. During this measurement, the output of the LVD is temporarily forced to low level so that false events, which may be caused by ADC reading, are discarded. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 5-19...
Page 152: Trimming
The dependence between POR and LVD on VDDREG is summarized in Figure 5-9. As shown, the LVD will reach a consistent state before the POR actually releases the reset, avoiding false startup condition. PXR40 Microcontroller Reference Manual, Rev. 1 5-20 Freescale Semiconductor...
Page 153 POR_B & LVI_B Overlap POR_B & LVI_B Overlap POR_B Asserts LVI_B Negates LVI_B Asserts LVI_B Asserts POR_B Asserts POR_B POR_B Negates LVI_B Indeterminate Indeterminate Figure 5-9. POR and LVD rising and falling edges PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 5-21...
Page 154: Adc Test Mux
LVD or regulator value. Vtarget is equal to: Vtarget=Vsupply*Vbg/Vadc. During LVD measurement, the continuous time monitoring is temporarily disabled as the multiplexer toggling could induce a false detection. PXR40 Microcontroller Reference Manual, Rev. 1 5-22 Freescale Semiconductor...
Page 155: Initialization
The bypass transistor VRCCTL MUST be operated out of saturation region. VDD12 Mandatory decoupling capacitor network *VRCCTL capacitor: may or may not be required Figure 5-10. VRC 1.2V LDO configuration with external bipolar PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 5-23...
Page 156: Hardware Design Recommendations
Ceramic -One capacitor for each VDD pin capacitor 20µF Supply decoupling cap (close to bipolar collector) capacitor 2.2uF Snubber cap, required with NJD2874 (on bipolar base) resistor 12 Ohm ESR for snubber cap PXR40 Microcontroller Reference Manual, Rev. 1 5-24 Freescale Semiconductor...
Page 157 6 x 0.1uF - 20V Ceramic -One capacitor for each VDD pin C3225X7R1E106M capacitor 2X10uF - 25V Supply decoupling cap - close to n-MOS drain resistor 20 kOhm Pull down for power n-MOS gate PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 5-25...
Page 158 Power Management Controller (PMC) PXR40 Microcontroller Reference Manual, Rev. 1 5-26 Freescale Semiconductor...
Page 159: Introduction
 X = divide-by-X, depending on SIU_SYSDIV[BYPASS] (D_CLKOUT is not available and SIU_SYSDIV[SYSCLKDIV]. on all packages and cannot be programmed for faster than fsys/2.) Figure 6-1. PXR40 Block Operating Frequency Domain Diagram PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 160: Frequency Modulated Phase-Locked Loop (Fmpll)
192 MHz – 600 MHz • PLL Off mode (low-power mode) • Register programmable output clock divider (ERFD) • Programmable frequency modulation — Modulation applied as a triangle waveform — Peak-to-peak register programmable modulation depths PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 161: Modes Of Operation
The table lists registers in the order of their addresses, identified by complete name and mnemonic, and the type of their accesses. Table 6-1. FMPLL Memory Map Offset from FMPLL_BASE_ADDR Register Bits Access Reset Value Section/Page (0xC3F8_0000) 0x0000 Reserved 0x0004 SYNSR—FMPLL synthesizer status register — 6.3.2.1/6-4 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 162: Register Descriptions
These bits may read 0 or 1, depending on current state of the PLL, however they do not provide any useful user information. Table 6-2. SYNSR Bit Field Descriptions Field Description 0–21 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 163 PLL mode. This bit is cleared in PLL Off mode. The value of ESYNCR1[CLKCFG0] is reflected in this location. 0 External clock reference chosen 1 Crystal clock reference chosen Note: The PLL controls the oscillator.. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 164 1 or asserting reset. A loss-of-clock condition can only be detected if LOCEN = 1. 0 Interrupt service not requested. 1 Interrupt service requested. 30–31 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 165: Fmpll Enhanced Synthesizer Control Register 1 (Esyncr1)
FM operation. Before changing EPREDIV, FM must be disabled and then reconfigured after the PLL re-locks to the new EPREDIV value. To prevent an immediate reset, clear the LOLRE bit before writing the EPREDIV bits. In PLL Off mode, the EPREDIV bits have no effect. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 166 4 (default if PLLCFG[2]=1) 0100 0101 0110 Invalid 0111 1000 Invalid 1001 1010–1111 Invalid Table 6-5. Feedback Divide Ratios EMFD Feedback Divide Ratio (EMFD+16) 0000_0000–0001_1111 Invalid 0010_0000 48 (default for PXR40) 0010_0001 0010_0010 0010_0011 0010_0100 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 167: Fmpll Enhanced Synthesizer Control Register 2 (Esyncr2)
When operating in normal PLL mode, the PLL must be locked before setting the LOLRE bit. Otherwise reset is immediately asserted. The LOLRE bit has no effect in PLL Off mode. 0 Assert reset on loss of lock is disabled. 1 Assert reset on loss of lock. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 168 FM operation. The sequence for enabling and configuring FM operation is described in Section 6.4.3.4.2, Programming System Clock Frequency With Frequency Modulation. This program sequence must be followed exactly to insure proper operation of the FM. 24–25 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 6-10 Freescale Semiconductor...
Page 169 Invalid Table 6-8. Output Divide Ratios ERFD Output Divide Ratio (ERFD+1) 00_0000 Divide-by-1 00_0001 Divide-by-2 00_0010 Invalid 00_0011 Divide-by-4 00_0100 Invalid 00_0101 Divide-by-6 00_0110 Invalid 00_0111 Divide-by-8 (default value for PXR40) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 6-11...
Page 170: Fmpll Synthesizer Fm Control Register (Synfmcr)
FMDAC_CTL. The ESYNCR2[EDEPTH] field must also be set to a non-zero value to enable FM. 0 FMDAC_CTL disabled. 1 FMDAC_CTL enabled. DAC is controlled by the value in FMDAC_CTL. 2–10 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 6-12 Freescale Semiconductor...
Page 171 However, the user may program intermediate values to trim the FM percentage for a specific application if desired. Do not program FMDAC_CTL to any value that will cause the system frequency to exceed the maximum specification. 16–0 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 6-13...
Page 172: Functional Description
When normal PLL mode is selected, the PLL is fully programmable. The PLL can synthesize frequencies ranging from 48x to 148x the reference frequency of the output of the predivider, with or without PXR40 Microcontroller Reference Manual, Rev. 1 6-14 Freescale Semiconductor...
Page 173: Pll Lock Detection
In PLL Off mode, the PLL cannot lock because the PLL is disabled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 6-15...
Page 174: Loss-Of-Clock Detection
LOCEN. The PLL output clocks are derived from the alternate clock source until reset is asserted. The alternate clock source used is dependent on whether the LOC is PXR40 Microcontroller Reference Manual, Rev. 1 6-16 Freescale Semiconductor...
Page 175: Pll Normal Mode Without Fm
After phase lock is achieved, the PFD continues to pulse the UP and DOWN signals for a very short duration during each reference clock cycle. These short pulses PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 6-17...
Page 176 EMFD factor that can be paired with an ERFD factor to provide the desired frequency. The maximum EMFD value that can be used is determined by the VCO and EMFD range. PXR40 Microcontroller Reference Manual, Rev. 1 6-18 Freescale Semiconductor...
Page 177: Pll Normal Mode With Frequency Modulation
Table 6-8, respectively. The modulation waveform is always a triangle wave and its shape is not programmable. An example of one period of the modulation waveform is shown in Figure 6-8. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 6-19...
Page 178 Even numbered ERFD settings, which would result in odd divide ratios, are invalid and cause the PLL to produce an unpredictable output clock. The PLL output clock must be within the f specification PXR40 Microcontroller Reference Manual, Rev. 1 6-20 Freescale Semiconductor...
Page 179 Finally, the error due to the manufacturing and environment variation alone can cause the frequency modulation depth error to be greater than 20%. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 6-21...
Page 180: Resets
After the initial lock with the default divider settings (assuming Normal Mode was selected), you may write to the SYNCR/ESYNCR(s) to modify the dividers for the desired operating frequency. The PLL may PXR40 Microcontroller Reference Manual, Rev. 1 6-22 Freescale Semiconductor...
Page 181: Pll Loss-Of-Lock Reset
When a loss-of-clock condition is recognized, the PLL requests an interrupt if the LOCIRQ bit in the SYNCR is set. The LOCIRQ bit has no effect in PLL Off mode or if LOCEN is equal to 0. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 6-23...
Page 182 Frequency Modulated Phase-Locked Loop (FMPLL) PXR40 Microcontroller Reference Manual, Rev. 1 6-24 Freescale Semiconductor...
Page 183: System Integration Unit (Siu)
• MCU reset configuration • System reset operation • Pad configuration • External interrupts • General-purpose I/O (GPIO) • Internal peripheral multiplexing • GPDI and GPDO I/Os of the DSPI modules PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 184: Block Diagram
DSPI signals I/O channels Figure 7-1. SIU Block Diagram NOTE The power-on reset detection module, pad interface/pad ring module, and peripheral I/O channels shown shaded in Figure 7-1 are external to the SIU. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 185: Overview
In normal mode, the SIU provides the register interface and logic that controls the device and system configuration, the reset controller, and GPIO. The SIU continues operation with no changes in stop mode. Debug SIU operation in debug mode is identical to operation in normal mode. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 186: External Signal Description
DDEH below the switch point value for more than two clock cycles. The switch point value is between the maximum V and minimum V specifications for the V input pins. DDEH PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 187: Boot Configuration (Bootcfg[0:1])
Table 7-4. BOOTCFG Configuration BOOTCFG[0] BOOTCFT[1] Meaning Boot from internal flash memory (default) FlexCAN / eSCI boot Boot from external memory (no arbitration) Boot from external memory (external arbitration) –EBI not available on all packages PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 188: I/O Weak Pullup Reset Configuration (Wkpcfg)
External Interrupt Request Input (IRQ) IRQ[0:15] The external interrupt request (IRQ) inputs connect to the SIU IRQ inputs. The external IRQ Input Select Register (SIU_EIISR) specifies the IRQ[0:15] signals that are input to the SIU IRQs. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 189: Memory Map And Register Definition
GPIO pin data output registers 0–511 SIU_BASE + (0x0800–0x08FF) SIU_GPDI0 – SIU_GPDI255— GPIO 0x00 7.3.1.15/7-40 input data registers 0–255 (Legacy support only, new implementation at SIU_BASE + 0x0E00) SIU_BASE + (0x0900–0x0903) Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 190 0–15 SIU_BASE + SIU_PGPDI0 – SIU_PGPDI15— 0x0000_0000 7.3.1.31/7-74 (0x0C40–0x0C7C) Parallel GPIO Pin Data input Register 0–15 SIU_BASE + SIU_MPGPDO0 – SIU_MPGPDO31— 0x0000_0000 7.3.1.32/7-75 (0x0C80–0x0CFC) Masked Parallel GPIO Pin Data Output Register 0–31 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 191 SIU_ETPUAC—DSPIC eTPUA Select 0x0000_0000 7.3.1.33.4/7-82 Register SIU_BASE+0x0D64 SIU_EMIOSC—DSPIC eMIOS Select 0x0000_0000 7.3.1.33.4/7-82 Register SIU_BASE+0x0D68 SIU_DSPICHLC—DSPIC 0x0000_0000 7.3.1.33.4/7-82 SIU_DSPICH/L Select Register SIU_BASE+0x0D6C SIU_ETPUBC—DSPIC eTPUB Select 0x0000_0000 7.3.1.33.4/7-82 Register SIU_BASE+0x0D70 SIU_ETPUBD—DSPID eTPUB Select 0x0000_0000 7.3.1.34/7-84 Register PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 192: Register Descriptions
The current value applies to revision 0 and is updated for each mask revision. The MCU ID register is 32 bits. Figure 7-2 shows the MCU ID register values. PXR40 Microcontroller Reference Manual, Rev. 1 7-10 Freescale Semiconductor...
Page 193: Reset Status Register (Siu_Rsr)
Simultaneous reset requests are prioritized. When reset requests with different priorities occur on the same clock cycle, the reset request with the highest priority is serviced and the status bit of only that reset request is set. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-11...
Page 194 The reset value of the WKPCFG bit is the value on the WKPCFG pin at the time of the last reset. The reset value of the BOOTCFG bits is the value on the BOOTCFG[0:1] pins at the time of the last reset. Figure 7-3. Reset Status Register (SIU_RSR) PXR40 Microcontroller Reference Manual, Rev. 1 7-12 Freescale Semiconductor...
Page 195 1 The WKPCFG pin value latched during the last reset was a logical 1 and weak pullup is the default setting. 17–27 Reserved Auto Baud Rate 0 Auto Baud Rate Disabled 1 Auto Baud Rate Enabled PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-13...
Page 196 More than one reset request occurred on the same clock cycle with no reset request by a higher-priority reset source, therefore the status bits for all the requesting resets are set. Refer to Table 7-7. PXR40 Microcontroller Reference Manual, Rev. 1 7-14 Freescale Semiconductor...
Page 197: System Reset Control Register (Siu_Srcr)
The external interrupt status register is used to record edge-triggered events on the IRQ[0]–IRQ[15] inputs to the SIU and record the critical interrupts NMI and SWT. When an edge-detect enable bit is set in the PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-15...
Page 198: Dma/Interrupt Request Enable Register (Siu_Direr)
DMA transfer request. The SIU uses one interrupt request to the interrupt controller. The EIRE bits determine the external interrupt requests that assert the SIU interrupt request to the interrupt controller. PXR40 Microcontroller Reference Manual, Rev. 1 7-16 Freescale Semiconductor...
Page 199: Dma/Interrupt Request Select Register (Siu_Dirsr)
IRQ flag bits are set in the external IRQ status register (SIU_EISR) and the DMA/interrupt request enable register (SIU_DIRER), then the select bit in the DMA interrupt request select register (SIU_DIRSR) determines whether a DMA or interrupt request is asserted. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-17...
Page 200: Overrun Status Register (Siu_Osr)
7.3.1.7 Overrun Status Register (SIU_OSR) The SIU_OSR flag bits indicate that an overrun has occurred. Address: SIU_BASE + 0x0020 Access: R/W Reset R OVF Reset Figure 7-8. Overrun Status Register (SIU_OSR) PXR40 Microcontroller Reference Manual, Rev. 1 7-18 Freescale Semiconductor...
Page 201: Overrun Request Enable Register (Siu_Orer)
Overrun request enable n. Enables the overrun request when an overrun occurs on the IRQ[n] pin. Bit 31 (ORE0) OREn is the enable overrun flag for IRQ[0]; bit 16 (ORE15) is overrun flag for IRQ[15]. 0 Overrun request is disabled. 1 Overrun request is enabled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-19...
Page 202: Irq Rising-Edge Event Enable Register (Siu_Ireer)
1 Rising-edge event is enabled. 1–15 Reserved 16–0 IRQ rising-edge event enable n. Enables rising-edge-triggered events on the corresponding IRQ[n] pin. IREEn 0 Rising-edge event is disabled. 1 Rising-edge event is enabled. PXR40 Microcontroller Reference Manual, Rev. 1 7-20 Freescale Semiconductor...
Page 203: Irq Falling-Edge Event Enable Register (Siu_Ifeer)
1 Rising-edge event is enabled. 1–15 Reserved 16–0 IRQ falling-edge event enable n. Enables falling-edge-triggered events on the corresponding IRQ[n] pin. IFEEn 0 Falling-edge event is disabled. 1 Falling-edge event is enabled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-21...
Page 204: Irq Digital Filter Register (Siu_Idfr)
IRQ input pins with the system clock. 7.3.1.12 IRQ Filtered Input Register (SIU_IFIR) The SIU_IFIR is a read only register where the filtered values of the NMI and IRQ[0]–IRQ[15] pins are captured. PXR40 Microcontroller Reference Manual, Rev. 1 7-22 Freescale Semiconductor...
Page 205 0 A logic zero has passed through the IRQ digital filter for the corresponding IRQ pin. 1 A logic one has passed through the IRQ digital filter for the corresponding IRQ pin. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-23...
Page 206: Pad Configuration Registers (Siu_Pcr)
Address: SIU_BASE + offset (see SIU_PCRn Settings table) Access: User read/write WPE WPS Reset See SIU_PCRn Settings table for reset values Figure 7-14. Pad Configuration Register (SIU_PCRn) PXR40 Microcontroller Reference Manual, Rev. 1 7-24 Freescale Semiconductor...
Page 207 0 Disable open drain for the pad (push/pull driver enabled). 1 Enable open drain for the pad. Input hysteresis. Controls whether hysteresis is enabled for the pad. 0 Disable hysteresis for the pad. 1 Enable hysteresis for the pad. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-25...
Page 208 WKPCFG pin does not determine the reset weak pullup/down state. 0 Pulldown is enabled for the pad. 1 Pullup is enabled for the pad. PXR40 Microcontroller Reference Manual, Rev. 1 7-26 Freescale Semiconductor...
Page 209 IRQ2 — IRQ3 — IRQ4 — IRQ5 — PCSB0 — SCKC — SINC — PCSC0 SCKD — SIND — PCSD0 — CANRXD — TXDA RXDA TXDB — RXDB — FR_RX_A — PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-27...
Page 210 Table 7-22. SIU_PCRn Settings SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 0x00D6 GPIO75 MDO4 — — — — — — — — — — — — 0x00D8 GPIO76 MDO5 — — — — — — —...
Page 211 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 0x0102 GPIO97 PCSA1 — — — — — — — 0x0104 GPIO98 PCSA2 — — — — — — — 0x0106 GPIO99 PCSA3 —...
Page 212 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 122 0x0134 GPIO122 ETPUA8 ETPUA20 — — — — — 123 0x0136 GPIO123 ETPUA9 ETPUA21 — — — — — 124 0x0138 GPIO124 ETPUA10 ETPUA22 —...
Page 213 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 145 0x0162 GPIO145 ETPUA31 PCSC4 — — — — — 146 0x0164 GPIO146 TCRCLKB IRQ6 — — — — — 147 0x0166 GPIO147 ETPUB0 ETPUB16 —...
Page 214 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 168 0x0190 GPIO168 ETPUB21 — — — — — — — 169 0x0192 GPIO169 ETPUB22 — — — — — — — 170 0x0194 GPIO170 ETPUB23 —...
Page 215 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 191 0x01BE GPIO191 EMIOS12 SOUTC — — — — — 192 0x01C0 GPIO192 EMIOS13 SOUTD — — — — — 193 0x01C2 GPIO193 EMIOS14 IRQ0 CNTXD...
Page 216 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 222 0x01FC GPIO222 MDO2 — — — — — — 223 0x01FE GPIO223 MDO3 — — — — — — 224 0x0200 — MSEO0 —...
Page 217 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 245 0x022A GPIO245 RXDC — — — — — — — 246 0x022C GPIO246 CNTXD — — — — — — — 247 0x022E GPIO247 CNRXD —...
Page 218 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 270 0x025C GPIO270 D_ADD23 D_ADD_DAT23 — — — — — 271 0x025E GPIO271 D_ADD24 D_ADD_DAT24 — — — — — 272 0x0260 GPIO272 D_ADD25 D_ADD_DAT25 —...
Page 219 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 293 0x028A GPIO293 D_ADD_DAT15 — — — — — — — 294 0x028C GPIO294 D_RD_WR — — — — — — — 295 0x028E GPIO295 D_WE0 —...
Page 220 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 442 0x03B4 GPIO442 — — — — — — — — 443 0x03B6 GPIO443 — — — — — — — — 444 0x03B8 GPIO444 —...
Page 221 Table 7-22. SIU_PCRn Settings (continued) SIU_PCRn[3:15] (SIU_PCRn[0:2] = Reserved, should be cleared) Address Primary GPIO Offset Function 465 0x03E2 GPIO465 — PCSD4 MAA1 MAB1 — — 466 0x03E4 GPIO466 — PCSD3 MAA2 MAB2 — — 467 0x03E6 GPIO467 — PCSD2 —...
Page 222: Gpio Pin Data Output Registers 0-512 (Siu_Gpdon)
GPDI[n] pin. The n notation in the SIU_GPDIn register name relates to the [n] in GPIO[n] signal name. For example, SIU_GPDI246 contains the PDI246 bit for CNTXD_GPIO246. The PXR40 Microcontroller Reference Manual, Rev. 1 7-40 Freescale Semiconductor...
Page 223: External Irq Input Select Register (Siu_Eiisr)
Address: SIU_BASE + 0x0904 Access: R/W ESEL15 ESEL14 ESEL13 ESEL12 ESEL11 ESEL10 ESEL9 ESEL8 Reset ESEL7 ESEL6 ESEL5 ESEL4 ESEL3 ESEL2 ESEL1 ESEL0 Reset Figure 7-17. External IRQ Input Select Register (SIU_EIISR) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-41...
Page 224 11 DSPI_D[10] deserialized input 16–17 External IRQ input select 7. Specifies the input for IRQ[7]. ESEL7 00 IRQ[7] pin 01 DSPI_B[7] deserialized input 10 DSPI_C[8] deserialized input 11 DSPI_D[9] deserialized input PXR40 Microcontroller Reference Manual, Rev. 1 7-42 Freescale Semiconductor...
Page 225: Dspi Input Select Register (Siu_Disr)
The SIU_DISR specifies the following operations for each DSPI: • Data input source • Slave select • Clock input Trigger input to allow serial and parallel chaining of the DSPI modules. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-43...
Page 226 00 No Trigger 01 PCSB[4] 10 PCSC[4] 11 PCSD[4] 8–9 DSPI B data input select. Specifies the source of DSPI B data input. SINSELB 00 SINB_GPIO[103] pin 01 SOUTA 10 SOUTC 11 SOUTD PXR40 Microcontroller Reference Manual, Rev. 1 7-44 Freescale Semiconductor...
Page 227 01 PCSA[4] 10 PCSB[4] 11 PCSD[4] 24–25 DSPI D data input select. Specifies the source of the DSPI D data input. SINSELD 00 PCSA[3]_GPIO[99] pin 01 SOUTA 10 SOUTB 11 SOUTC PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-45...
Page 228: Eqadc Command Fifo Trigger Source Select - Imux Select Registers (Siu_Isel[4-7])
A command FIFO trigger input can be programmed to recognize either rising or falling edges, and low or high gated trigger types. SIU_ISEL4: eTRIG_A[5:2] Address: SIU_BASE + 0x0910 Access: R/ W cTSEL5_0 cTSEL4_0 Reset cTSEL3_0 cTSEL2_0 Reset PXR40 Microcontroller Reference Manual, Rev. 1 7-46 Freescale Semiconductor...
Page 229 Reset Reset SIU_ISEL6: eTRIG_B[5:2] Address: SIU_BASE + 0x0918 Access: R/ W cTSEL5_1 cTSEL4_1 Reset cTSEL3_1 cTSEL2_1 Reset SIU_ISEL7: eTRIG_B[1:0] Address: SIU_BASE + 0x091C Access: R/ W cTSEL1_1 cTSEL0_1 Reset Reset PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-47...
Page 230 Reserved eTRIG1 pin Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA30 eMIOS eMIOS10 eTRIG ETRIG0 Pin PXR40 Microcontroller Reference Manual, Rev. 1 7-48 Freescale Semiconductor...
Page 231 Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA31 eMIOS eMIOS11 eTRIG ETRIG1 Pin PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-49...
Page 232 Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA29 eMIOS eMIOS15 eTRIG ETRIG0 Pin PXR40 Microcontroller Reference Manual, Rev. 1 7-50 Freescale Semiconductor...
Page 233 Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA28 eMIOS eMIOS14 eTRIG ETRIG1 Pin PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-51...
Page 234 Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA27 eMIOS eMIOS13 eTRIG ETRIG0 Pin PXR40 Microcontroller Reference Manual, Rev. 1 7-52 Freescale Semiconductor...
Page 235 Reserved eTRIG0 pin Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA26 eMIOS eMIOS12 eTRIG ETRIG1 Pin PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-53...
Page 236 Reserved eTRIG1 pin Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA30 eMIOS eMIOS10 eTRIG ETRIG0 Pin PXR40 Microcontroller Reference Manual, Rev. 1 7-54 Freescale Semiconductor...
Page 237 Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA31 eMIOS eMIOS11 eTRIG ETRIG1 Pin PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-55...
Page 238 Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA29 eMIOS eMIOS15 eTRIG ETRIG0 Pin PXR40 Microcontroller Reference Manual, Rev. 1 7-56 Freescale Semiconductor...
Page 239 Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA28 eMIOS eMIOS14 eTRIG ETRIG1 Pin PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-57...
Page 240 Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA27 eMIOS eMIOS13 eTRIG ETRIG0 Pin PXR40 Microcontroller Reference Manual, Rev. 1 7-58 Freescale Semiconductor...
Page 241 Reserved eTRIG0 pin Reserved eTPUA28 eTPUA29 eTPUA30 eTPUA31 eTPUB28 eTPUB29 eTPUB30 eTPUB31 Reserved Reversed Reserved Reserved eMIOS16 eMIOS17 eMIOS18 eMIOS19 eMIOS20 eMIOS21 eMIOS22 eMIOS23 eTPU eTPUA26 eMIOS eMIOS12 eTRIG ETRIG1 Pin PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-59...
Page 242: Etpu Input Select Register (Siu_Isel 8)
0 DSPI_B Serialized input 11 eTPU26 1 eTPU26 channel input pad 24–26 Reserved eTPU25 input select. Specifies the source of the eTPU25 channel input. 0 DSPI_B Serialized input 12 eTPU25 1 eTPU25 channel input pad PXR40 Microcontroller Reference Manual, Rev. 1 7-60 Freescale Semiconductor...
Page 243: Eqadc Advance Trigger Selection (Siu_Isel9)
Table 7-40. eTSEL0A Bit Field Descriptions eTSEL0A eQADC Trigger Input Reserved RTI Trigger PIT0 Trigger PIT1 Trigger PIT2 Trigger PIT3 Trigger Reserved Reserved eTPUA30 AND PIT0 eTPUA30 AND PIT1 Reserved Reserved eTPUA28 eTPUA29 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-61...
Page 244: Decimation Filter Register 1 (Siu_Decfil1)
Decimation Filter, for more information on the ZIR and Halt operations in the decimation filter. Address: SIU_BASE + 0x0928 Access: R/W ZSELA HSELA ZSELB HSELB Reset ZSELC HSELC ZSELD HSELD Reset PXR40 Microcontroller Reference Manual, Rev. 1 7-62 Freescale Semiconductor...
Page 245 0100 eTPUB Channel 25 28–31 Halt Input Select for Decimation Filter D HSELD 0000 Unused 0001 eTPUB Channel 22 0010 eTPUB Channel 23 0011 eTPUB Channel 24 0100 eTPUB Channel 25 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-63...
Page 246: Decimation Filter Register 2 (Siu_Decfil2)
0100 eTPUA Channel 21 12–15 Halt Input Select for Decimation Filter F HSELF 0000 Unused 0001 eTPUA Channel 18 0010 eTPUA Channel 19 0011 eTPUA Channel 20 0100 eTPUA Channel 21 PXR40 Microcontroller Reference Manual, Rev. 1 7-64 Freescale Semiconductor...
Page 247 0100 eTPUB Channel 21 28–31 Halt Input Select for Decimation Filter H HSELH 0000 Unused 0001 eTPUB Channel 18 0010 eTPUB Channel 19 0011 eTPUB Channel 20 0100 eTPUB Channel 21 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-65...
Page 248: Chip Configuration Register (Siu_Ccr)
Do not change this bit from its negated state at reset. 0 Undocumented production test registers cannot be read or written. 1 Undocumented production test registers can be read or written. PXR40 Microcontroller Reference Manual, Rev. 1 7-66 Freescale Semiconductor...
Page 249: External Clock Control Register (Siu_Eccr)
0 External bus signals have zero output hold times. 1 External bus signals have non-zero output hold times. Note: Do not change EBTS while an external bus transaction is in process. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-67...
Page 250: Compare B Register High (Siu_Cbrh)
(0xFEED_FACE_CAFE_BEEF). The CMPBH field is read/write and is reset by the internal reset condition. Address: SIU_BASE + 0x0990 Access: R/W CMPBH Reset CMPBH Reset Figure 7-23. Compare B Register High (SIU_CBRH) PXR40 Microcontroller Reference Manual, Rev. 1 7-68 Freescale Semiconductor...
Page 251: Compare B Register Low (Siu_Cbrl)
CPU frequency 10 Reserved 11 CPU, eTPU, platform, and peripheral’s clocks all run at same speed (Max 132Mhz) Note: Refer to the PXR40 Microcontroller Data Sheet for the latest frequency specifications. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-69...
Page 252: Halt Register (Siu_Hlt)
Section Chapter 20, Periodic Interrupt Timer (PIT_RTI), for more information on how to use the SIU_HLT and SIU_HLTACK registers. Address: SIU_BASE + 0x9A4 Access: R/W RESET RESET Figure 7-26. Halt Register (SIU_HLT) PXR40 Microcontroller Reference Manual, Rev. 1 7-70 Freescale Semiconductor...
Page 253: Halt Acknowledge Register (Siu_Hltack)
The input signals from each module will be connected as shown in Table 7-47., HALT Acknowledge Register Field Descriptions. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-71...
Page 254 22 DSPI_B 23 DSPI_A 24 rsvd 25 rsvd 26 rsvd 27 rsvd 28 rsvd 29 eSCI_C 30 eSCI_B 31 eSCI_A Stops all CPU clocks, stops the platform, excluding interrupt controller and watchdogs. PXR40 Microcontroller Reference Manual, Rev. 1 7-72 Freescale Semiconductor...
Page 255: Parallel Gpio Pin Data Output Register (Siu_Pgpdo0 - Siu_Pgpdo15)
7.3.1.30 Parallel GPIO Pin Data Output Register (SIU_PGPDO0 - SIU_PGPDO15) The PGPDOx registers are written to by software to drive data out on the external GPIO pin. These registers access the same GPIO pins accessed by SIU_GPDO0–SIU_GPDO511 bit registers. The SIU_GPDO registers should map directly to these registers. For example, SIU_PGPDO0 bit 31 is SIU_GPDO31 bit 7, SIU_PGPDO0 bit 30 is SIU_GPDO30 bit 7,.., SIU_PGPD07 bit 0 is SIU_GPDO224 bit 7.
Page 256: Parallel Gpio Pin Data Input Register (Siu_Pgpdi0 - Siu_Pgpdi15)
PGPDI PGPDI RESET: PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI PGPDI RESET: Figure 7-29. Parallel GPIO Pin Data Input Register (SIU_PGPDI0 - SIU_PGPDI15) PXR40 Microcontroller Reference Manual, Rev. 1 7-74 Freescale Semiconductor...
Page 257: Masked Parallel Gpio Pin Data Output Register (Siu_Mpgpdo0 - Siu_Mpgpdo31)
1 Logic high value is driven on the pad interface data out signal for the corresponding GPIO pin when the pin is configured as an output. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-75...
Page 258: Siu Dspi Serialization Registers
32-bit registers, one for each module that is mapped plus one for the data register. An example of how these registers are used to create the DSPI serialized output is shown below. PXR40 Microcontroller Reference Manual, Rev. 1 7-76 Freescale Semiconductor...
Page 259 DSPIA Output Register Frame bit 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Function & Channel Selection PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-77...
Page 260 SIU_BASE + 0x0D74 -SIU_BASE + 0x0D77 DSPID eMIOS Select Register SIU_BASE + 0x0D78 -SIU_BASE + 0x0D7B DSPID GPO Select Register SIU_BASE + 0x0D7C -SIU_BASE + 0x0D7F Reserved SIU_BASE + 0x0D80 -SIU_BASE + 0x0DC0 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 7-78 Freescale Semiconductor...
Page 261 Each register bit enables a path from the eTPU_B channel, eMIOS channel and data register bit SIU_DSPIAH/SIU_DSPIAL to the equivalent bit position in the DSPI_A serialized output frame. The user must ensure that bit selections from each of these registers do not overlap. Multiple sources are PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-79...
Page 262 0 This bit in the DSPI_A serialized output frame will not use the respective EMIOS channel 1 This bit in the DSPI_A serialized output frame will use the respective EMIOS channel PXR40 Microcontroller Reference Manual, Rev. 1 7-80 Freescale Semiconductor...
Page 263 0 This bit in the DSPI_B serialized output frame will not use the respective ETPUA channel 1 This bit in the DSPI_B serialized output frame will use the respective ETPUA channel PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-81...
Page 264 Multiple sources are logically ORed, which provides the potential for combining outputs from multiple timer channels and data registers to produce more complex bit behavior. PXR40 Microcontroller Reference Manual, Rev. 1 7-82 Freescale Semiconductor...
Page 265 0 This bit in the DSPI_C serialized output frame will not use the respective EMIOS channel 1 This bit in the DSPI_C serialized output frame will use the respective EMIOS channel PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-83...
Page 266: Serialized Output Signal Selection Registers For Dspi_D
DSPI_D serialized output frame. The user must ensure that bit selections from each of these registers do not overlap. Multiple sources are logically ORed, which provides the potential for combining outputs from multiple timer channels and data registers to produce more complex bit behavior. PXR40 Microcontroller Reference Manual, Rev. 1 7-84 Freescale Semiconductor...
Page 267 0 This bit in the DSPI_D serialized output frame will not use the respective EMIOS channel 1 This bit in the DSPI_D serialized output frame will use the respective EMIOS channel SIU_BASE + 0xD78 RESET: RESET: Figure 7-45. DSPIDH/L Select Register for DSPI_D (SIU_DSPIDHLD) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-85...
Page 268: Gpio Pin Data Input Registers (Siu_Gpdi0_3 - Siu_Gpdi508_511) - Standard
Each byte of a register represents the input state of a single external GPIO pin. The first 256 GPDIx_x registers corresponds to the same GPDI inputs described in Section 7.3.1.15, GPIO Pin Data Input Registers 0–255 (SIU_GPDIn). SIU_BASE+0x0E00 PDI0 RESET: Figure 7-46. GPIO Pin Data In Register 0 (SIU_GPDI0) PXR40 Microcontroller Reference Manual, Rev. 1 7-86 Freescale Semiconductor...
Page 269: Functional Description
Data direction selection The pad configuration registers are provided to allow centralized control over external pins that are shared by more than one module. Each pad configuration register controls a single pin. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-87...
Page 270: Reset Control
• Previous filtered IRQ state was a logic 0 • Current latched IRQ state is a logic 1 • Rising-edge event is enabled for the IRQ PXR40 Microcontroller Reference Manual, Rev. 1 7-88 Freescale Semiconductor...
Page 271 When the ‘DMA done’ signal asserts, the IRQ flag bit is cleared. Refer to the following sections for more information: • Section 7.3.1.5, DMA/Interrupt Request Enable Register (SIU_DIRER) • Section 7.3.1.6, DMA/Interrupt Request Select Register (SIU_DIRSR) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-89...
Page 272 Refer to the following sections for more information: • Section 7.3.1.4, External Interrupt Status Register (SIU_EISR) • Section 7.3.1.9, IRQ Rising-Edge Event Enable Register (SIU_IREER) • Section 7.3.1.10, IRQ Falling-Edge Event Enable Register (SIU_IFEER) PXR40 Microcontroller Reference Manual, Rev. 1 7-90 Freescale Semiconductor...
Page 273: Gpio Operation
DSPI signals used for chaining serial and parallel DSPI modules A block diagram of the internal multiplexing feature is shown in Figure 7-49. The figure shows the multiplexing of four external signals to an SIU output. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-91...
Page 274: Eqadc External Trigger Input Multiplexing
All ETRIG inputs are multiplexed in the same manner. If an eTPU or eMIOS channel is selected as an ETRIG input to the eQADC, you can activate the alternate function of that eTPU or eMIOS signal on the external pin. PXR40 Microcontroller Reference Manual, Rev. 1 7-92 Freescale Semiconductor...
Page 275: Siu External Interrupt Input Multiplexing
Each DSPI module can be combined in a serial or parallel chain (multiple transfer operation). Serial chaining allows SPI operation with an external device that has more bits than one DSPI module. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-93...
Page 276 An example of a parallel chain is shown in Figure 7-53. DSPI C (slave) DSPI B (master) SOUT SOUT Trigger MTRIG PCS[0] SCK IN SCK IN SOUT External SPI device Figure 7-52. DSPI Serial Chaining PXR40 Microcontroller Reference Manual, Rev. 1 7-94 Freescale Semiconductor...
Page 277 System Integration Unit (SIU) DSPI A (master) DSPI B (slave) SOUT SOUT Trigger MTRIG PCS[0] SCK IN SOUT SCK IN SCK IN SOUT External SPI device External SPI device Figure 7-53. DSPI Parallel Chaining PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 7-95...
Page 278 System Integration Unit (SIU) PXR40 Microcontroller Reference Manual, Rev. 1 7-96 Freescale Semiconductor...
Page 279: System Information Module
Temperature sensor calibration constant 0x08 Reserved 0x0C 0x10 Unique Device ID 0x14 Unique Device ID 0x18 Unique Device ID 0x1C Unique Device ID 0x20 Reserved 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 280 System Information Module PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 281: Boot Assist Module (Bam)
Controls MCU core Watchdog Timer and/or the Software Watchdog Timer (SWT) Modes of Operation 9.3.1 Normal Mode The BAM program is executed immediately following the negation of RESET. 1. EBI not available on all packages. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 282: Debug Mode
BAM address map. Table 9-1. BAM Memory Map Address Description 0xFFFF_C000 – 0xFFFF_EFFF BAM program mirrored 0xFFFF_F000 – 0xFFFF_FFFF BAM program 0xFFFF_FFFC MCU reset vector 0xFFFF_FFF8 BAM last executed instruction PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 283: Functional Description
Search for RCHW Configure MMU for EBI boot Found RCHW? Check RCHW Found Parse RCHW RCHW? and execute RCHW options Exit To User Code Figure 9-1. BAM program Flow Chart PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 284: Bam Program Operation
Nexus port can be enabled or disabled, the password received in the serial boot mode is compared with the fixed public password or compared to a user programmable password in the internal flash memory. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 285 Censorship control field–default value configures the device as uncensored. Address: 0x00FF_FDE2 Value: 0x55AA Binary value Hex value Serial boot control field–default value reads a password from internal flash. Figure 9-2. Censorship Word PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 286: Reset Configuration Half Word (Rchw)
RCHW locations in the internal flash. When booting from the external flash device, the RCHW must reside in the first 16 bit half word of the flash. BOOT_BLOCK_ADDRESS SWT WTE Boot Identifier = 0x5A Figure 9-4. Reset Configuration Half Word PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 287 Table 9-5. Watchdog Timeout vs. Crystal Frequency Crystal Frequency (MHz) Core WD Timeout (ms) SWT Timeout (ms) 27.3 18.3 32.7 13.7 24.5 19.6 With the PLL in normal mode and crystal oscillator as a reference clock source. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 288: Application Start Address Register
When serial boot mode is detected, either because of the BOOTCFG configuration or because a valid RCHW word was not found in any of the expected locations in the Flash, the BAM program does the following: PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 289 TXD_A GPIO GPIO — GPIO — TXD_A Push/Pull output, with medium slew rate RXD_A GPIO RXD_A Input with pull-up and GPIO — RXD_A Input with pull-up and hysteresis hysteresis PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor...
Page 290: Can Controller Configuration In The Fixed Baud Rate Mode
11 bit identifier format detailed in CAN 2.0A specification. See Table 9-8 for examples of baud rates. Only one message buffer 0 is used for all communications. The bit timing is configured as shown in Figure 9-6. PXR40 Microcontroller Reference Manual, Rev. 1 9-10 Freescale Semiconductor...
Page 291: Sci Controller Configuration In Fixed Baud Rate Mode
A message with 0x12 ID and 8-byte length to send the start address, length, and the VLE mode bit. The MCU transmits back the same data, but with ID of 0x2. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 9-11...
Page 292: Download Protocol Execution
The two least significant bits of the start address are ignored by the BAM program, thus the loaded code should be 32-bit word aligned. – CODE_LENGTH defines how many data bytes to be loaded. PXR40 Microcontroller Reference Manual, Rev. 1 9-12 Freescale Semiconductor...
Page 293 – disables software watchdog (SWT) Table 9-8 for examples of time out periods. The BAM code passes control to the loaded code at START_ADDRESS, which was received in step 2 of the protocol. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 9-13...
Page 294: Baud Rate Detection Procedure
The CAN baud rate depends on the number of quantas per bit and serial clock frequency, which is defined by a prescaler. The CAN baud rate detection routine selects these parameters to maximize number of PXR40 Microcontroller Reference Manual, Rev. 1 9-14 Freescale Semiconductor...
Page 295 112.5K 17.2 3750 150K 4687.5 187.5K 28.6 When the MCU operates with the PLL in normal mode with crystal oscillator as a reference clock source. Limited by 1Mbps by CAN standard PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 9-15...
Page 296: Booting From The Development Bus
Set pads to 20pf drive strength and pull-up enable SIU_PCR295 D_WE0 SIU_PCR297 D_OE SIU_PCR298 D_TS RCHW[PS0] must be programmed to “1”, since the development bus does not support 32-bit port size in that sub-mode. PXR40 Microcontroller Reference Manual, Rev. 1 9-16 Freescale Semiconductor...
Page 297: Ebi Configuration For Multiplexed Address And Data Development Bus Boot Mode
When the debug port is enabled on a censored device, it is enabled only until the next reset. Figure 9-8 shows the logic that enables access to Nexus clients in a censored device using the JTAG port. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 9-17...
Page 298 / calibration tool is not able to access the device. After the debug port is enabled, the tool can access the censored device and can erase and reprogram the shadow flash block in order to uncensor the device. PXR40 Microcontroller Reference Manual, Rev. 1 9-18 Freescale Semiconductor...
Page 299 4. Subsequent resets will clear the JTAG censor password register and the Nexus client TAP controller will hold in reset again. Therefore, the tool must resend the JTAG serial password, as described above, in order to enable the Nexus client TAP controller again. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 9-19...
Page 300 Boot Assist Module (BAM) PXR40 Microcontroller Reference Manual, Rev. 1 9-20 Freescale Semiconductor...
Page 301: Interrupts And Interrupt Controller (Intc)
Although N (largest addressable IRQ vector number) = 479, this does not indicate the total number of interrupts available on this device. The total number of available interrupts on this device is 480: 410 peripheral IRQs, 8 software-configurable IRQs, and 62 reserved. Figure 10-1. INTC Block Diagram PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-1...
Page 302: Overview
Interrupts Available Software Watchdog Memory eDMA FMPLL External IRQ input pins (SIU) eMIOS eTPU engine A eTPU engine B eQADC DSPI eSCI FlexCAN FlexRay Decimation Filter System (PIT, RTI, PMC, etc.) PXR40 Microcontroller Reference Manual, Rev. 1 10-2 Freescale Semiconductor...
Page 303 IRQs, and 62 reserved. In hardware vector mode, the core branches to an interrupt exception handler unique for each interrupt request source. Typical program flow for hardware vector mode is shown in Figure 10-4. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-3...
Page 304: Features
9-bit unique vector for each interrupt request source in hardware vector mode. • Each interrupt source can be programmed to one of 16 priorities. • Preemption. — Preemptive prioritized interrupt requests to processor. PXR40 Microcontroller Reference Manual, Rev. 1 10-4 Freescale Semiconductor...
Page 305: Modes Of Operation
The interrupt request to the processor does not clear if a higher priority interrupt request arrives. Even in this case, INTVEC does not update to the higher priority request until the lower priority PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-5...
Page 306: Hardware Vector Mode
However, the interrupt request to the processor do not negate if a higher priority interrupt request arrives. Even in this case, the interrupt vector number does not update to the higher priority request until the lower priority request is acknowledged by the processor. PXR40 Microcontroller Reference Manual, Rev. 1 10-6 Freescale Semiconductor...
Page 307: External Signal Description
0x0000_000F 10.3.1.2/10-1 Base + 0x000C Reserved Base + 0x0010 INTC_IACKR—INTC interrupt acknowledge 0x0000_0000 10.3.1.3/10-1 register Base + 0x0014 Reserved Base + 0x0018 INTC_EOIR—INTC end-of-interrupt register 0x0000_0000 10.3.1.4/10-1 Base + 0x001C Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-7...
Page 308 When the HVEN bit in the INTC_MCR is asserted, a read of the INTC_IACKR has no side effects. The PRI fields are “Reserved” for peripheral interrupt requests whose vectors are labeled as Reserved in Table 10-7. PXR40 Microcontroller Reference Manual, Rev. 1 10-8 Freescale Semiconductor...
Page 309: Register Descriptions
Hardware vector enable. Controls whether the INTC is in hardware vector mode or software vector mode. Refer to HVEN Section 10.1.4, Modes of Operation, for the details of the handshaking with the processor in each mode. 0 Software vector mode 1 Hardware vector mode PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-9...
Page 310: Intc Current Priority Register (Intc_Cpr)
The reading also pushes the PRI value in the INTC current priority register (INTC_CPR) onto the LIFO and updates PRI in the INTC_CPR with the priority of the interrupt request. The side effect PXR40 Microcontroller Reference Manual, Rev. 1 10-10 Freescale Semiconductor...
Page 311: Intc End-Of-Interrupt Register (Intc_Eoir)
Writing to the INTC_EOIR signals the end of the servicing of the interrupt request. When the INTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR. The values and size of data PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-11...
Page 312: Intc Software Set/Clear Interrupt Registers (Intc_Sscir0-7)
Clear flag bits. CLRn is the flag bit. Writing a 1 to CLRn clears it provided that a 1 is not written simultaneously to its CLRn corresponding SETn bit. Writing a 0 to CLRn has no effect. 0 Interrupt request not pending within INTC. 1 Interrupt request pending within INTC. PXR40 Microcontroller Reference Manual, Rev. 1 10-12 Freescale Semiconductor...
Page 313: Intc Priority Select Registers (Intc_Psr0-479)
Interrupt requests from the same module location are ORed together. The individual interrupt priorities are selected in INTC_PSRn, where the priority select register is assigned according to the vector number. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-13...
Page 314 10 0x0160 EDMA_IRQRL[INT11] eDMA_A channel interrupt 11 0x0170 EDMA_IRQRL[INT12] eDMA_A channel interrupt 12 0x0180 EDMA_IRQRL[INT13] eDMA_A channel interrupt 13 0x0190 EDMA_IRQRL[INT14] eDMA_A channel interrupt 14 0x01A0 EDMA_IRQRL[INT15] eDMA_A channel interrupt 15 PXR40 Microcontroller Reference Manual, Rev. 1 10-14 Freescale Semiconductor...
Page 315 SIU_EISR[EIF15:EIF4] SIU external interrupt flags 15–4 eMIOS 0x0330 EMIOS_GFR[F0] eMIOS channel 0 flag 0x0340 EMIOS_GFR[F1] eMIOS channel 1 flag 0x0350 EMIOS_GFR[F2] eMIOS channel 2 flag 0x0360 EMIOS_GFR[F3] eMIOS channel 3 flag PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-15...
Page 316 A channel 11 interrupt status 0x0500 ETPU_CISR_A[CIS12] eTPU engine A channel 12 interrupt status 0x0510 ETPU_CISR_A[CIS13] eTPU engine A channel 13 interrupt status 0x0520 ETPU_CISR_A[CIS14] eTPU engine A channel 14 interrupt status PXR40 Microcontroller Reference Manual, Rev. 1 10-16 Freescale Semiconductor...
Page 317 A command FIFO 1 pause flag 0x06C0 EQADC_FISR1[EOQF] eQADC A command FIFO 1 command queue end-of-queue flag 0x06D0 EQADC_FISR1[CFFF] eQADC A command FIFO 1 fill flag 0x06E0 EQADC_FISR1[RFDF] eQADC A receive FIFO 1 drain flag PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-17...
Page 318 DSPI C combined overrun interrupt requests: DSPI_CSR[TFUF] • Transmit FIFO underflow DSPI_CSR[RFOF] • Receive FIFO overflow 0x0890 DSPI_CSR[EOQF] DSPI C transmit FIFO end-of-queue flag 0x08A0 DSPI_CSR[TFFF] DSPI C Tx FIFO Fill request PXR40 Microcontroller Reference Manual, Rev. 1 10-18 Freescale Semiconductor...
Page 319 • Physical bus error ESCIA_IFSR2[CERR] • CRC error ESCIA_IFSR2[CKERR] • Checksum error ESCIA_IFSR2[FRC] • Frame complete interrupts requests ESCIA_IFSR2[OVFL] • Receive register overflow ESCIA_IFSR2[UREQ] • Unrequested data received 0x0930–0x0940 147–148 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-19...
Page 320 FlexCAN A buffer 7 interrupt 0x0A30 CANA_IFRL[BUF8] FlexCAN A buffer 8 interrupt 0x0A40 CANA_IFRL[BUF9] FlexCAN A buffer 9 interrupt 0x0A50 CANA_IFRL[BUF10] FlexCAN A buffer 10 interrupt 0x0A60 CANA_IFRL[BUF11] FlexCAN A buffer 11 interrupt PXR40 Microcontroller Reference Manual, Rev. 1 10-20 Freescale Semiconductor...
Page 321 FlexCAN C buffer 15 interrupt 0x0C00 CANC_IFRL[BUF31:BUF16] FlexCAN C buffers 31–16 interrupts 0x0C10 CANC_IFRH[BUF63:BUF32] FlexCAN C buffers 63–32 interrupts 0x0C20–0x0C40 194–196 Reserved Decimation Filter A 0x0C50 DEC_A Decimation Filter A input (fill) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-21...
Page 322 41 0x0DD0 EDMA_IRQRH[INT42] eDMA_A channel interrupt 42 0x0DE0 EDMA_IRQRH[INT43] eDMA_A channel interrupt 43 0x0DF0 EDMA_IRQRH[INT44] eDMA_A channel interrupt 44 0x0E00 EDMA_IRQRH[INT45] eDMA_A channel interrupt 45 0x0E10 EDMA_IRQRH[INT46] eDMA_A channel interrupt 46 PXR40 Microcontroller Reference Manual, Rev. 1 10-22 Freescale Semiconductor...
Page 323 B channel 9 interrupt status 0x0FD0 ETPU_CISR_B[CIS10] eTPU engine B channel 10 interrupt status 0x0FEO ETPU_CISR_B[CIS11] eTPU engine B channel 11 interrupt status 0x0FF0 ETPU_CISR_B[CIS12] eTPU engine B channel 12 interrupt status PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-23...
Page 324 DSPI_A Rx FIFO drain request flag FlexCAN B 0x1180 CANB_ESR[BOFF_INT] FlexCAN B bus off interrupt CANB_ESR[TWRN_INT] FlexCAN B transmit warning interrupt CANB_ESR[RWRN_INT] FlexCAN B receive warning interrupt 0x1190 CANB_ESR[ERR_INT] FlexCAN B error interrupt 0x11A0 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 10-24 Freescale Semiconductor...
Page 325 ECC Correction FlexCAN D 0x1340 CAND_ESR[BOFF_INT] FlexCAN D bus off interrupt CAND_ESR[TWRN_INT] FlexCAN D transmit warning interrupt CAND_ESR[RWRN_INT] FlexCAN D receive warning interrupt 0x1350 CAND_ESR[ERR_INT] FlexCAN D error interrupt 0x1360 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-25...
Page 326 FlexRay WUP_IF 0x1620 GIFER[FBNE_F] FlexRay FBNE_F 0x1630 GIFER[FANE_F] FlexRay FANE_F 0x1640 GIFER[RBIF] FlexRay RBIF 0x1650 GIFER[TBIF] FlexRay TBIF 0x1660–0x16D0 358–365 Reserved Decimation Filter B 0x16E0 DEC_B Decimation Filter B input (fill) PXR40 Microcontroller Reference Manual, Rev. 1 10-26 Freescale Semiconductor...
Page 327 B receive FIFO 9 drain flag 0x19F0 EQADC_FISR4[NCF] eQADC B command FIFO 10 non-coherency flag 0x1A00 EQADC_FISR4[PF] eQADC B command FIFO 10 pause flag 0x1A10 EQADC_FISR4[EOQF] eQADC B command FIFO 10 command queue end-of-queue flag PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-27...
Page 328 16 0x1BB0 EDMA_IRQRL[INT17] eDMA_B channel interrupt 17 0x1BC0 EDMA_IRQRL[INT18] eDMA_B channel interrupt 18 0x1BD0 EDMA_IRQRL[INT19] eDMA_B channel interrupt 19 0x1BE0 EDMA_IRQRL[INT20] eDMA_B channel interrupt 20 0x1BFO EDMA_IRQRL[INT21] eDMA_B channel interrupt 21 PXR40 Microcontroller Reference Manual, Rev. 1 10-28 Freescale Semiconductor...
Page 329 0x1D50 DEC_C Decimation Filter C error Decimation Filter D 0x1D60 DEC_D Decimation Filter D input (fill) 0x1D70 DEC_D Decimation Filter D output (drain) 0x1D80 DEC_D Decimation Filter D error eSCI C PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-29...
Page 330 If this occurs, the processor uses the INTC_PSRn value to locate the IRQ vector, and updates the PRIn value in the INTC_CPR with the PRIn value in INTC_PSRn. PXR40 Microcontroller Reference Manual, Rev. 1 10-30 Freescale Semiconductor...
Page 331: Peripheral Interrupt Requests
The asserted interrupt requests are compared to each other based on their PRIn values in INTC priority select registers (INTC_PSR0–INTC_PSR479). The result of that comparison also is compared to PRI in PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-31...
Page 332: Current Priority And Preemption
INTC_IACKR_PRC1 with the vector number of the first interrupt that arrives that has a priority higher than the current priority. Once the vector number and priority are captured, they cannot be superseded by a higher priority interrupt until an update of the INTC_CPR_PRC0 or INTC_CPR_PRC1 occurs. PXR40 Microcontroller Reference Manual, Rev. 1 10-32 Freescale Semiconductor...
Page 333: Lifo
The INTVEC field retains that value until the next time the interrupt request to the processor is asserted. The rest of the handshaking is described in Section 10.1.4.1, Software Vector Mode. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-33...
Page 334: Hardware Vector Mode Handshaking
INTC examines the peripheral and software configurable interrupt requests, and when it finds an asserted one with a higher priority than PRI in INTC_CPR, it asserts the interrupt request PXR40 Microcontroller Reference Manual, Rev. 1 10-34 Freescale Semiconductor...
Page 335: Initialization And Application Information
PRIn fields in INTC_PSRn set the enable bits or clear the mask bits for the peripheral interrupt requests lower PRI in INTC_CPR to zero enable processor recognition of interrupts PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-35...
Page 336: Interrupt Exception Handler
ISR for interrupt with vector 510 address of ISR for interrupt with vector 511 ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC # return to epilog PXR40 Microcontroller Reference Manual, Rev. 1 10-36 Freescale Semiconductor...
Page 337: Hardware Vector Mode
If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-37...
Page 338: Order Of Execution
INTC_EOIR. Interrupt taken. ISR208 starts to execute, even though peripheral interrupt request 300 asserted first. ISR208 completes. Interrupt exception handler writes to INTC_EOIR. Interrupt taken. ISR308 starts to execute. PXR40 Microcontroller Reference Manual, Rev. 1 10-38 Freescale Semiconductor...
Page 339: Priority Ceiling Protocol
If INTC asserts the ISR2 interrupt request to the processor just before or at the same time as the first ISR1 write, it is possible for both the ISR1 and ISR2 writes to execute while the processor responds to the INTC PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-39...
Page 340 The example is for software vector mode, but except for the method of retrieving the vector and acknowledging the interrupt request to the processor, hardware vector mode is identical. PXR40 Microcontroller Reference Manual, Rev. 1 10-40 Freescale Semiconductor...
Page 341 LIFO pops 3, restoring the raised priority onto PRI in INTC_CPR. Next value to pop from LIFO is the priority from before peripheral interrupt request 100 interrupted. ISR108 now can access data block coherently after interrupt exception handler executes rfi instruction. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-41...
Page 342: Selecting Priorities According To Request Rates
(INTC_SSCIR0–INTC_SSCIR7). Writing a 1 to SETn causes a software configurable interrupt request. This software configurable interrupt request, which usually has a lower PRIn value in the INTC_PSRn, therefore does not cause preemptive scheduling inefficiencies. PXR40 Microcontroller Reference Manual, Rev. 1 10-42 Freescale Semiconductor...
Page 343: Scheduling An Isr On Another Processor
For example, reading a specific register can clear the flag bits, and consequently their corresponding interrupt requests too. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-43...
Page 344: Negating Multiple Interrupt Requests In One Isr
INTC_CPR[PRI] onto the LIFO, therefore the LIFO contents cannot be restored in hardware vector mode. push_lifo: load stacked PRI value and store to INTC_CPR load INTC_IACKR if stacked PRI values are not depleted, branch to push_lifo PXR40 Microcontroller Reference Manual, Rev. 1 10-44 Freescale Semiconductor...
Page 345 However, since the peripheral or software configurable interrupt requests are not cleared, the peripheral interrupt request to the processor re-asserts when INTC_CPR[PRI] is lower than the priorities of those peripheral or software configurable interrupt requests. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 10-45...
Page 346 Interrupts and Interrupt Controller (INTC) PXR40 Microcontroller Reference Manual, Rev. 1 10-46 Freescale Semiconductor...
Page 347: General-Purpose Static Ram (Sram)
External Signal Description The external signal for SRAM is the V RAM power supply. If the standby feature of the SRAM is STBY not used, tie the V pin to V STBY PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 11-1...
Page 348: Register Memory Map
3. The ECC is then calculated on the resulting 64 bits formed in the previous step. 4. The 8-bit ECC result is appended to the 64 bits from the data bus, and the 72-bit value is then written to SRAM. PXR40 Microcontroller Reference Manual, Rev. 1 11-2 Freescale Semiconductor...
Page 349: Access Timing
Pipelined read Read Idle Pipelined read 1,0,0,0 Burst read 64-bit write 2,0,0,0 Burst read 0,0,0,0 (read from the same address) 8-, 16-, or 32-bit write 1,0,0,0 (read from a different address) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 11-3...
Page 350: Reset Effects On Sram Accesses
If the write is not the entire 64-bits (8-, 16-, or 32-bits), a read / modify / write operation is generated that checks the ECC value upon the read. See Section 11.6, SRAM ECC Mechanism. NOTE You must initialize SRAM, even if the application does not use ECC reporting. PXR40 Microcontroller Reference Manual, Rev. 1 11-4 Freescale Semiconductor...
Page 351: Example Code
# write all 32 GPRs to SRAM addi r11,r11,128 # inc the ram ptr; 32 GPRs * 4 bytes = 128 bdnz init_ram_loop # loop for 256K of SRAM # done PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 11-5...
Page 352 General-Purpose Static RAM (SRAM) PXR40 Microcontroller Reference Manual, Rev. 1 11-6 Freescale Semiconductor...
Page 353: Flash Memory Array And Control
Each flash array has three address spaces: low-address space, mid-address space, and high-address space that are subdivided into blocks as shown in Figure 12-1. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-1...
Page 354: Block Diagram
Program execution and data fetches from the Flash module are performed through the FBIU. Control and status registers, used for flash memory reprogramming purposes are accessed through PBRIDGE_A. PXR40 Microcontroller Reference Manual, Rev. 1 12-2 Freescale Semiconductor...
Page 355: Features
Configurable access timing allowing use in a wide range of system frequencies. • Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) allowing use for emulation of other memory types. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-3...
Page 356: Modes Of Operation
There are no program-visible registers that physically reside in the flash. The flash controller contains the registers to control and configure the flash (see Table 12-3). Only reference these registers with 32-bit accesses. PXR40 Microcontroller Reference Manual, Rev. 1 12-4 Freescale Semiconductor...
Page 357 0x00E0_0000 to 0x00EF_FFFF and Shadow A mirrors every 16K from 0x00F0_0000 through 0x00FF_FFFF. Mirrored operation is not guaranteed Flash_A and Flash_B arrays have separate configuration and control registers for programming and erase operations. Flash bus configuration registers are common to both arrays. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-5...
Page 358 0x0014 FLASH_A_HSR—High-address space block select 0x0000_0000 12.2.2.6/12-18 register 0x0018 FLASH_A_AR—Address register 0x0000_0000 12.2.2.7/12-18 0x001C FLASH_BIUCR—Flash Bus Interface configuration 0x0000_FF00 12.2.2.8/12-19 register 0x0020 FLASH_BIUAPR—Flash Bus Interface access 0xFFFF_FFFF 12.2.2.9/12-22 protection register PXR40 Microcontroller Reference Manual, Rev. 1 12-6 Freescale Semiconductor...
Page 359: Register Descriptions
In the following register descriptions, the letter “x” represents “A” for Flash_A registers, and “B” for Flash_B registers. Registers without the “x” designator are common to both arrays and are used to control the flash bus interface. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-7...
Page 360: Module Configuration Register (Flash_X_Mcr)
EER) are correct. Since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. A write of 0 has no effect. 0 Reads are occurring normally. 1 An ECC Error occurred during a previous read. PXR40 Microcontroller Reference Manual, Rev. 1 12-8 Freescale Semiconductor...
Page 361 Note: If program or erases are attempted on blocks that are locked, the response from flash is PEG = 1, indicating that the operation was successful, and the contents of the block are properly protected from the program or erase operation. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-9...
Page 362 (PGM is low and UTE is low). ERS can be cleared by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0 Flash is not executing an erase sequence. 1 Flash is executing an erase sequence. PXR40 Microcontroller Reference Manual, Rev. 1 12-10 Freescale Semiconductor...
Page 363 The flash module does not allow the user to write bits simultaneously which put the device into an illegal state. This is implemented through a priority mechanism among the bits. The bit changing priorities are detailed in Table 12-5. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-11...
Page 364: Low/Mid Address Space Block Locking Register (Flash_X_Lmlr)
0 0 0 0 0 0 0 0 0 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* Figure 12-4. FLASH_x_LMLR Register FLASH_x_LMLR register functions, as shown in Table 12-6. PXR40 Microcontroller Reference Manual, Rev. 1 12-12 Freescale Semiconductor...
Page 365 The reset value is always 1 (independent of the shadow block), and register writes have no effect. MLOCK is not writable unless LME is high. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-13...
Page 366: High Address Space Block Locking Register (Flash_X_Hlr)
Flash values in the shadow block. An erased shadow block causes the reset value to be 1. The following field and bit descriptions fully define the FLASH_x_HLR register (Figure 12-5). PXR40 Microcontroller Reference Manual, Rev. 1 12-14 Freescale Semiconductor...
Page 367 The block numbering for High Address Space is given in the table below, and is the same for Flash_A and Flash_B. HLOCK Bit Flash_A Block Flash_B Block HLOCK is not writable unless HBE is high. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-15...
Page 368: Secondary Low/Mid Address Space Block Locking Register (Flash_X_Slmlr)
Secondary Shadow Lock. This bit is an alternative method that may be used to lock the shadow block SSLOCK from programs and erases. SSLOCK has the same description as SLOCK in the FLASH_x_LMLR register (see Figure 12-4). SSLOCK is not writable unless SLE is high. 12–13 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 12-16 Freescale Semiconductor...
Page 369: Low/Mid Address Space Block Select Register (Flash_X_Lmsr)
The reset value is always 0, and register writes have no effect. MSEL bits are mapped to block numbers in the same way as described for the MLOCK bits of the FLASH_x_LMLR register. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-17...
Page 370: High Address Space Block Select Register (Flash_X_Hsr)
The Address register (FLASH_x_AR) provides the first failing address in the event module failures (ECC or PGM/Erase state machine). This address is the internal array address. To convert to a logical system address, a formula must be applied: PXR40 Microcontroller Reference Manual, Rev. 1 12-18 Freescale Semiconductor...
Page 371: Flash Bus Interface Configuration Register (Flash_Biucr)
FLASH_x_MCR[PEG] does not affect the writability of the FLASH_x_AR. 29–31 Reserved 12.2.2.8 Flash Bus Interface Configuration Register (FLASH_BIUCR) FLASH_BIUCR is used to specify operation of the dual-flash controller. This register must not be written while executing from flash. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-19...
Page 372 110 Access requests require six additional hold cycles 111 No address pipelining Note: The settings for APC and RWSC must be the same. Note: Valid settings are specified in product Data Sheet. PXR40 Microcontroller Reference Manual, Rev. 1 12-20 Freescale Semiconductor...
Page 373 0 The line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers are successfully filled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-21...
Page 374: Flash Bus Interface Access Protection Register (Flash_Biuapr)
Note: These bits refer to the master ID, not the master port number, as shown in the following: Master ID Module Z7 Core – reserved – – reserved – – reserved – eDMA_A eDMA_B FlexRay Reserved for EBI test (not for customer use) Z7 Nexus PXR40 Microcontroller Reference Manual, Rev. 1 12-22 Freescale Semiconductor...
Page 375: Flash Bus Interface Configuration Register 2 (Flash_Biucr2)
10 The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11 The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. 2–31 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-23...
Page 376: User Test Register 0 (Flash_X_Ut0)
This register is only writable when the flash is put into UTest mode by writing a passcode. Offset: 0x003C / 0x403C Access: User read/write UTE SCBE Reset Reset Figure 12-14. User Test Register 0 (FLASH_x_UT0) PXR40 Microcontroller Reference Manual, Rev. 1 12-24 Freescale Semiconductor...
Page 377 It should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary sequence. If MRE is set, AIS has no effect. 0 Array integrity sequence is proprietary sequence. 1 Array integrity sequence is sequential. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-25...
Page 378 Once completed, AID is set to indicate that the array integrity check is complete. At this time the MISR (UMR registers) can be checked. AID can not be written, and is status only. 0 Array integrity check is ongoing. 1 Array integrity check is done. PXR40 Microcontroller Reference Manual, Rev. 1 12-26 Freescale Semiconductor...
Page 379: User Test Register 1 (Flash_X_Ut1)
Data Array Input. These bits enable checks of ECC logic by allowing data bits to be input into the ECC logic and then read out by doing array reads or array integrity checks. The DAI[63:32] correspond to the 32 Array bits representing Word 1of the double word selected in the FLASH_x_AR. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-27...
Page 380: Functional Description
The shadow block is included to support systems that require NVM for security or system initialization information. PXR40 Microcontroller Reference Manual, Rev. 1 12-28 Freescale Semiconductor...
Page 381: Flash Programming
9. Write a logic 0 to the FLASH_x_MCR[PGM] bit to terminate the program sequence. The program sequence is presented graphically in Figure 12-17. The program suspend operation detailed Figure 12-17 is discussed in Section 12.3.4.1.1, Flash Program Suspend/Resume. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-29...
Page 382 The user may not abort a program sequence while in program suspend. NOTE Aborting a program operation will leave the flash core addresses being programmed in an indeterminate data state. This may be recovered by executing an erase on the affected blocks. PXR40 Microcontroller Reference Manual, Rev. 1 12-30 Freescale Semiconductor...
Page 383 Note: PEG will remain valid under this condition until EHV is set high or PGM is cleared. Step 9 Write MCR PGM = 0 ESUS User mode read state Erase suspend Figure 12-17. Program Sequence PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-31...
Page 384: Software Locking
FLASH_x_LMSR or FLASH_x_HSR. If the shadow row is to be erased, this step may be skipped, and FLASH_x_LMSR and FLASH_x_HSR are ignored. For shadow row erase, see section Section 12.3.6, Flash Shadow Block, for more information. PXR40 Microcontroller Reference Manual, Rev. 1 12-32 Freescale Semiconductor...
Page 385: Flash Erase Suspend/Resume
Programming locations in blocks targeted for erase during erase-suspended program may result in corrupted data. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-33...
Page 386 This can extend the time required for the erase operation. CAUTION In an erase-suspended program, programming flash locations in blocks which were being operated on in the erase may corrupt flash core data. PXR40 Microcontroller Reference Manual, Rev. 1 12-34 Freescale Semiconductor...
Page 387: Flash Shadow Block
The user must terminate the shadow erase operation to program or erase the main address space. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 12-35...
Page 388: Flash Reset
After reset is negated, register accesses can be performed, although it should be noted that registers that require updating from shadow information, or other inputs, cannot read updated until flash exits reset. PXR40 Microcontroller Reference Manual, Rev. 1 12-36 Freescale Semiconductor...
Page 389: Core (E200Z7) Overview
The figures below show the complete PXR40 register set for Supervisor and User Modes. The number to the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (XER) is SPR 1). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-1...
Page 390 1 - These PXR40-specific registers may not be supported L1CFG0 SPR 515 by other PowerPC processors SPR 1016 L1FINV0 2 - Optional registers defined by the PowerPC Book-E L1CFG1 SPR 516 architecture SPR 959 L1FINV1 3 - Read-only registers PXR40 Microcontroller Reference Manual, Rev. 1 13-2 Freescale Semiconductor...
Page 391 PMR 259 PMLCb3 UPMLCb3 PMR 2 UPMC2 PMR 3 UPMC3 1 - These PXR40-specific registers may not be supported by other PowerPC processors Cache Access Registers DCR 351 CDACNTL DCR 350 CDADATA PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-3...
Page 392: Cache
If the access does not match a valid cache tag entry (misses in the cache) or a write access must be written through to memory, the cache performs a bus cycle on the system bus. PXR40 Microcontroller Reference Manual, Rev. 1 13-4 Freescale Semiconductor...
Page 393: Cache Registers
Bit 7 corresponds to way 3. The WDD bits may be used for locking ways of the data cache, and also are used in determining the replacement policy of the data cache. 8–10 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-5...
Page 394 Indicates a lock set instruction was not effective in locking a cache line. This bit is set DCUL by hardware on an “unable to lock” condition (other than lock overflows), and will remain set until cleared by software writing 0 to this bit location. PXR40 Microcontroller Reference Manual, Rev. 1 13-6 Freescale Semiconductor...
Page 395 Indicates a Cache Invalidate or a Cache Lock Bits Flash Clear operation was aborted DCABT prior to completion. This bit is set by hardware on an aborted condition, and will remain set until cleared by software writing 0 to this bit location. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-7...
Page 396: L1 Cache Control And Status Register 1 (L1Csr1)
The L1CSR1 bits are described below. Table 13-2. L1CSR1 Field Descriptions Field Description 0–14 Reserved Instruction Cache Error Checking Enable 0 Error Checking is disabled ICECE 1 Error Checking is enabled PXR40 Microcontroller Reference Manual, Rev. 1 13-8 Freescale Semiconductor...
Page 397 In parity mode, tag or lock errors will result in invalidation of lines. Correction is performed for single or multi-bit data errors by reloading of the line. 1x Reserved 27–28 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-9...
Page 398: L1Finv0
6–7 Cache Way CWAY Specifies the data cache way to be selected 8–19 Reserved for set extension 20–26 Cache Set CSET Specifies the cache set to be selected PXR40 Microcontroller Reference Manual, Rev. 1 13-10 Freescale Semiconductor...
Page 399: L1Finv1
These bits are not implemented and should be written with zero for future compatibility. 13.4 This section lists the most commonly used registers, instructions, and features of MMU. For a complete listing of all registers and features refer to z759n3 Core Reference Manual. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-11...
Page 400: Overview
The TLB read entry instruction causes the content of a single TLB entry to be placed in the MMU assist registers. The entry is specified by the TLBSEL and ESEL fields of the MAS0 register. The entry contents are placed in the MAS1, MAS2, and MAS3 registers. PXR40 Microcontroller Reference Manual, Rev. 1 13-12 Freescale Semiconductor...
Page 401: Tlb Write Entry Instruction (Tlbwe)
The TLB write entry instruction causes the contents of certain fields within the MMU assist registers MAS1, MAS2, and MAS3 to be written into a single TLB entry in the MMU. The entry written is specified by the TLBSEL, and ESEL fields of the MAS0 register. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-13...
Page 402: Mmu Registers
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 1012; Read/ Write; Reset - 0x0 Figure 13-6. MMU Control and Status Register 0 (MMUCSR0) The MMUCSR0 bits are described below. PXR40 Microcontroller Reference Manual, Rev. 1 13-14 Freescale Semiconductor...
Page 403: Mmu Assist Registers (Mas)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 624; Read/ Write; Reset - Unaffected Figure 13-7. MMU Assist Register 0 (MAS0) Fields are defined below. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-15...
Page 404 This field is compared with the current process IDs of the effective address to be translated. A TID value of 0 defines an entry as global and matches with all process IDs. 16–18 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 13-16 Freescale Semiconductor...
Page 405 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 626; Read/ Write; Reset - Unaffected Figure 13-9. MMU Assist Register 2 (MAS2) Fields are defined below. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-17...
Page 406 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 627; Read/ Write; Reset - Unaffected Figure 13-10. MMU Assist Register 3 (MAS3) PXR40 Microcontroller Reference Manual, Rev. 1 13-18 Freescale Semiconductor...
Page 407 00 PID0 14–15 01 Reserved, do not use TIDSELD 10 Reserved, do not use 11 TIDZ (8’h00)) (Use all zeros, the globally shared value) 16–19 Reserved 20–24 Default TSIZE value TSIZED Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-19...
Page 408: Exceptions
These bits are not implemented, will be read as zero, and writes are ignored. 13.5 Exceptions This section provides an overview of core exceptions. For detailed explanation see z759n3 Core Reference Manual. PXR40 Microcontroller Reference Manual, Rev. 1 13-20 Freescale Semiconductor...
Page 409: Exception Syndrome Register
Data Cache Locking Data Storage Instruction Cache Locking Data Storage Reserved — Unimplemented Operation exception Program Byte Ordering exception Data Storage Mismatched Instruction Storage exception Instruction Storage Reserved 16–23 Reserved — PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-21...
Page 410: Machine State Register
0 - Execution of the cache locking instructions in user mode (MSR =1) disabled; DSI UCLE exception taken instead, and ILK or DLK set in ESR. 1 - Execution of the cache lock instructions in user mode enabled. PXR40 Microcontroller Reference Manual, Rev. 1 13-22 Freescale Semiconductor...
Page 411 0 - The processor directs all instruction fetches to address space 0 (TS=0 in the relevant TLB entry). 1 - The processor directs all instruction fetches to address space 1 (TS=1 in the relevant TLB entry). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-23...
Page 412: Machine Check Syndrome Register (Mcsr)
Hardware will not clear a bit in the MCSR other than at reset. Note that any set bit in the MCSR other than status-type bits will cause a subsequent machine check interrupt once MSR PXR40 Microcontroller Reference Manual, Rev. 1 13-24 Freescale Semiconductor...
Page 413 Error Precise An error occurred during the attempt to fetch an Report instruction. This could be due to a parity error, or an external bus error. MCSRR0 contains the instruction address. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-25...
Page 414 MSR =1. If MSR =0, the machine check exception will remain pending. These bits will remain set until cleared by software writing a “1” to the bit position(s) to be cleared. PXR40 Microcontroller Reference Manual, Rev. 1 13-26 Freescale Semiconductor...
Page 415: Interrupt Vector Prefix Registers (Ivpr)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 400-415, 528-530; Read/Write Figure 13-16. PXR40 Interrupt Vector Offset Register (IVOR) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-27...
Page 416: Interrupt Definitions
|| p_voffset[0:11] || 4b0000 (non-autovectored) 0:15 DE is cleared when the Debug APU is disabled. Clearing of DE is optionally supported by control in HID0 when the Debug APU is enabled. PXR40 Microcontroller Reference Manual, Rev. 1 13-28 Freescale Semiconductor...
Page 417: Machine Check Interrupt (Ivor1)
Updated to reflect the source(s) of a machine check. Hardware only sets appropriate bits, no previously set bits are cleared by hardware. MCAR Vector IVPR || IVOR1 || 4b0000 0:15 16:27 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-29...
Page 418: Data Storage Interrupt (Ivor2)
For Access and Byte ordering exceptions, set to the effective address of a byte within the page whose access caused the violation. Undefined on Cache locking exceptions (DEAR is not updated on a cache locking exception) Vector IVPR || IVOR2 || 4b0000 0:15 16:27 PXR40 Microcontroller Reference Manual, Rev. 1 13-30 Freescale Semiconductor...
Page 419: Instruction Storage Interrupt (Ivor3)
If input is negated early, recognition of the interrupt request is not guaranteed. When the core detects the exception, if the exception is enabled by MSR , it takes the External Input interrupt. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-31...
Page 420: Alignment Interrupt (Ivor5)
Execution of a dcbz instruction is attempted with a disabled cache. • Execution of a dcbz instruction with an enabled cache and W or I =1. • Execution of a SPE APU load or store instruction which is not properly aligned. PXR40 Microcontroller Reference Manual, Rev. 1 13-32 Freescale Semiconductor...
Page 421: Program Interrupt (Ivor6)
The PXR40 will invoke a Trap exception on execution of the tw and twi instructions if the trap conditions are met and the exception is not also enabled as a Debug interrupt. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-33...
Page 422: Floating-Point Unavailable Interrupt (Ivor7)
SRR1 Set to the contents of the MSR at the time of the interrupt UCLE 0 SPE 0 — — — PMM 0 — [VLEMI] All other bits cleared. MCSR Unchanged PXR40 Microcontroller Reference Manual, Rev. 1 13-34 Freescale Semiconductor...
Page 423: 10Auxiliary Processor Unavailable Interrupt (Ivor9)
The Timer Status Register (TSR) holds the FIT interrupt bit set by the Timer facility when an exception is detected. Software must clear this bit in the interrupt handler to avoid repeated FIT interrupts. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-35...
Page 424: 13Watchdog Timer Interrupt (Ivor12)
CSRR1 Set to the contents of the MSR at the time of the interrupt UCLE 0 SPE 0 — 0/— PMM 0 — Unchanged MCSR Unchanged PXR40 Microcontroller Reference Manual, Rev. 1 13-36 Freescale Semiconductor...
Page 425: Data Tlb Error Interrupt (Ivor13)
Table 13-29. Instruction TLB Error Interrupt—Register Settings Register Setting Description SRR0 Set to the effective address of the excepting instruction. SRR1 Set to the contents of the MSR at the time of the interrupt PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-37...
Page 426: 16Debug Interrupt (Ivor15)
There are multiple sources that can signal a Debug exception. A Debug interrupt occurs when no higher priority exception exists, a Debug exception exists in the Debug Status Register, and Debug interrupts are enabled (both DBCR0 =1 (internal debug mode) and MSR =1). PXR40 Microcontroller Reference Manual, Rev. 1 13-38 Freescale Semiconductor...
Page 427: Spe/Efpu Apu Unavailable Interrupt (Ivor32)
The SPE APU Unavailable exception is taken if MSR is cleared and execution of a SPE or EFPU APU instruction other than the scalar floating-point instructions or brinc is attempted. When the SPE/EFPU PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-39...
Page 428: Embedded Floating-Point Data Interrupt (Ivor33)
Set to the contents of the MSR at the time of the interrupt UCLE 0 SPE 0 — — — PMM 0 — SPE, [VLEMI]. All other bits cleared. MCSR Unchanged DEAR Unchanged Vector IVPR || IVOR33 || 4b0000 0:15 16:27 PXR40 Microcontroller Reference Manual, Rev. 1 13-40 Freescale Semiconductor...
Page 429: 19Embedded Floating-Point Round Interrupt (Ivor34)
Table 13-34. Performance Monitor Interrupt—Register Settings Register Setting Description SRR0 Set to the effective address of the next instruction to be executed. SRR1 Set to the contents of the MSR at the time of the interrupt PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-41...
Page 430: 13.10 Special Features
Wait instruction can be used in conjunction with the SIU_HALT mechanism and SIU_HLTACK registers to enter a low power state while waiting. Software must ensure that interrupts responsible for exiting the waiting state are enabled before executing a wait instruction. PXR40 Microcontroller Reference Manual, Rev. 1 13-42 Freescale Semiconductor...
Page 431: 2Volatile Context Save/Restore Apu
Characterize processors in environments not easily characterized by benchmarking. • Help system developers bring up and debug their systems. For a complete description of Performance Monitor see z759n3 Core Reference Manual. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 13-43...
Page 432 Core (e200z7) Overview PXR40 Microcontroller Reference Manual, Rev. 1 13-44 Freescale Semiconductor...
Page 433: Amba Crossbar Switch (Xbar)
The XBAR can place a slave port in a low-power park mode to avoid dissipating any power transitional address, control or data signals when the master port is not actively accessing the slave port. There is a one-cycle arbitration overhead for exiting low-power park mode. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 14-1...
Page 434: Block Diagram
This port is not usable by customers, but exists in the device. Therefore, the priority must be set to a unique value in the Master Priority Registers. 14.1.3 Features • Multiple master and slave ports with programmable priorities and attributes. PXR40 Microcontroller Reference Manual, Rev. 1 14-2 Freescale Semiconductor...
Page 435: Modes Of Operation
Base + 0x0210 XBAR_SGPCR2—General-purpose control 0x0000_0000 14.2.1.2/14-6 register for slave port 2 Base + (0x0214–0x05FF) Reserved Base + 0x0600 XBAR_MPR6—Master priority register for 0x7654_3210 14.2.1.1/14-4 slave port 6 Base + (0x0604–0x060F) Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 14-3...
Page 436: Register Descriptions
(RO) bit is set in the slave general-purpose control register, the master priority register can only be read. Attempts to write to it have no effect on the MPR and result in an error. NOTE XBAR_MPR must be written with a read/modify/write for code compatibility. PXR40 Microcontroller Reference Manual, Rev. 1 14-4 Freescale Semiconductor...
Page 437 000 Master 4 has the highest priority when accessing slave port n. 101 Master 4 has the lowest priority when accessing slave port n. 110–111 Invalid values 16-24 Reserved, must be cleared. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 14-5...
Page 438: Slave General-Purpose Control Registers (Xbar_Sgpcrn)
Some of the unused bits in the SGPCRn registers are writeable and readable, but they serve no function. Setting any of these bits has no effect on the operation of this module. PXR40 Microcontroller Reference Manual, Rev. 1 14-6 Freescale Semiconductor...
Page 439 10 LPP—Low-power park. When no master is making a request, the arbiter parks the slave port on no master and drives all slave port outputs to a safe state. 11 Invalid value PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 14-7...
Page 440 001 Park on master port 1 010 Invalid value 011 Invalid value 100 Park on master port 4 101 Park on master port 5 110 Park on master port 6 111 Invalid value PXR40 Microcontroller Reference Manual, Rev. 1 14-8 Freescale Semiconductor...
Page 441: Functional Description
This can avoid the initial clock of the arbitration delay if the master must arbitrate to gain control of the slave port. The slave port can also be put into low-power park mode to save power. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 14-9...
Page 442: Master Ports
(XBAR_MPR) undefined behavior results. 14.3.6 Arbitration XBAR supports two arbitration schemes; a simple fixed-priority comparison algorithm, and a round-robin fairness algorithm. The arbitration scheme is independently programmable for each slave port. PXR40 Microcontroller Reference Manual, Rev. 1 14-10 Freescale Semiconductor...
Page 443: Fixed Priority Operation
The round-robin pointer is reset to 0, so if master 1 has another request that occurs before master 0’s transfer completes, master 1 is the granted the bus. This implies a worst case latency of N transfers for a system with N masters. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 14-11...
Page 444 However, when a master does make a request to a slave port parked in low-power-park, a one clock arbitration delay is incurred to get ownership of the slave port. PXR40 Microcontroller Reference Manual, Rev. 1 14-12 Freescale Semiconductor...
Page 445: Introduction
• Override the privilege level of a master to change it to user mode privilege • Designate masters as trusted or untrusted Peripherals can implement the following restrictions: PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 15-1...
Page 446 — FMPLL — EBI control — Flash control — — eMIOS PBRIDGE A Slave 6 — — eTPU reg — eTPU PRAM — eTPU PRAM mirror — eTPU SCM — PIT_RTI PXR40 Microcontroller Reference Manual, Rev. 1 15-2 Freescale Semiconductor...
Page 447: Features
FlexRay — Temp Sensor — 15.1.3 Features The following list summarizes the key features of the PBRIDGE: • Supports the slave interface signals. This interface is only meant for slave peripherals. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 15-3...
Page 448: Modes Of Operation
1 Base + 0x0048 PBRIDGE_A_OPACR2—Off-platform 0x4444_4444 15.3.1.2/15-7 peripheral access control register 2 Base + 0x004C PBRIDGE_A_OPACR3—Off-platform 0x4444_4444 15.3.1.2/15-7 peripheral access control register 3 Base + (0x0050–0x0053) Reserved PXR40 Microcontroller Reference Manual, Rev. 1 15-4 Freescale Semiconductor...
Page 449 1 Base + 0x0048 PBRIDGE_B_OPACR2—Off-platform 0x4444_4444 15.3.1.2/15-7 peripheral access control register 2 Base + 0x004C PBRIDGE_B_OPACR3—Off-platform 0x4444_4444 15.3.1.2/15-7 peripheral access control register 3 Base + (0x0050–0x0053) Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 15-5...
Page 450: Register Descriptions
MBW4 MTR4 MTW4 MPL4 MBW5 MTR5 MTW5 MPL5 MBW6 MTR6 MTW6 MPL6 Reset Figure 15-2. Master Privilege Control Registers (PBRIDGE_x_MPCR) The following table describes the fields in the PBRIDGE master privilege control register: PXR40 Microcontroller Reference Manual, Rev. 1 15-6 Freescale Semiconductor...
Page 451 PACR register structure is shown in Table 15-2 Table 15-3. The PACR registers with their access fields are shown in Figure 15-3. There are three PACR registers, one for bridge A and two for bridge B. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 15-7...
Page 452 The default values are always used for the SP0 and TP0 bits, even though the bits are writeable. The default value is 0b0000 for PACR peripheral access fields that are unused or not connected. Figure 15-3. Peripheral Access Control Registers (PBRIDGE_x_PACRn) PXR40 Microcontroller Reference Manual, Rev. 1 15-8 Freescale Semiconductor...
Page 453 Note: For PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0, you must have supervisor privileges to access PBRIDGE registers. Note: Even though the SP0 bit (1) is writeable, the reset value for SP0 is always used. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 15-9...
Page 454 PBRIDGE A 0b0101 PBRIDGE_A_PACR0 PBRIDGE_A_Base + 0x0020 1–7 Reserved 0b0000 FMPLL 0b0100 EBI control 0b0100 Flash A control 0b0100 PBRIDGE_A_OPACR0 PBRIDGE_A_Base + 0x0040 Flash B control 0b0100 0b0100 5–7 Reserved 0b0100 PXR40 Microcontroller Reference Manual, Rev. 1 15-10 Freescale Semiconductor...
Page 455 PBRIDGE_B_OPACR0 PBRIDGE_B_Base + 0x0040 eQADC A 0b0100 eQADC B 0b0100 Decimation Filters A, 0b0100 B, C, D Reserved 0b0100 DSPI A 0b0100 DSPI B 0b0100 DSPI C 0b0100 DSPI D 0b0100 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 15-11...
Page 456 PBRIDGE_B_Base + 0x0048 FlexCAN A 0b0100 FlexCAN B 0b0100 FlexCAN C 0b0100 FlexCAN D 0b0100 4–7 Reserved 0b0100 PBRIDGE_B_OPACR3 PBRIDGE_B_Base + 0x004C FlexRay 0b0100 1–2 Reserved 0b0100 Temp Sensor 0b0100 Reserved 0b0100 0b0100 PXR40 Microcontroller Reference Manual, Rev. 1 15-12 Freescale Semiconductor...
Page 457: Functional Description
INTC_EOIR that consumes at least the number of system clock cycles that the actual write is delayed. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 15-13...
Page 458: Read Cycles
Off-platform module selects and control register storage do not have the same degree of configurability. PXR40 Microcontroller Reference Manual, Rev. 1 15-14 Freescale Semiconductor...
Page 459 PBRIDGE also supports buffered writes, allowing write accesses to be terminated on the system bus in a single clock cycle, and then subsequently performed on the slave interface. Write buffering is controllable on a per-peripheral basis. The PBRIDGE implements a two-entry 32-bit write buffer. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 15-15...
Page 460 Peripheral Bridge (PBRIDGE) PXR40 Microcontroller Reference Manual, Rev. 1 15-16 Freescale Semiconductor...
Page 461: Introduction
The MPU implements a set of program-visible region descriptors that monitor all system bus addresses. The result is a hardware structure with a two-dimensional connection matrix, where the region descriptors represent one dimension and the individual system bus addresses and attributes are the second dimension. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 16-1...
Page 462: Block Diagram
— Nexus 3 — eDMA_A — eDMA_B — FlexRay — On-chip Flash — — EBI (development bus) — On-chip SRAM — Peripheral bridge A (PBRIDGE_A) — Peripheral bridge B (PBRIDGE_B) — PXR40 Microcontroller Reference Manual, Rev. 1 16-2 Freescale Semiconductor...
Page 463: Features
AHB reference is terminated with an error response and the MPU inhibits the bus cycle being sent to the targeted slave device — 64-bit error registers, one for each AHB slave port, capture the last faulting address, attributes, and detail information PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 16-3...
Page 464: Memory Map And Registers
MPU_RGD5 — MPU region descriptor 5 — 16.2.2.4/16-8 0x0460 MPU_RGD6 — MPU region descriptor 6 — 16.2.2.4/16-8 0x0470 MPU_RGD7 — MPU region descriptor 7 — 16.2.2.4/16-8 0x0480 MPU_RGD8 — MPU region descriptor 8 — 16.2.2.4/16-8 PXR40 Microcontroller Reference Manual, Rev. 1 16-4 Freescale Semiconductor...
Page 465 MPU_RGDAAC12 — MPU RGD alternate access — 16.2.2.5/16-13 control 12 0x0834 MPU_RGDAAC13 — MPU RGD alternate access — 16.2.2.5/16-13 control 13 0x0838 MPU_RGDAAC14 — MPU RGD alternate access — 16.2.2.5/16-13 control 14 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 16-5...
Page 466: Register Descriptions
This field reads as 0 on this device. 16–19 Number of MPU ports. This 4-bit read-only field specifies the number of slave ports connected to the MPU. This field reads as 0b0100 on this device. PXR40 Microcontroller Reference Manual, Rev. 1 16-6 Freescale Semiconductor...
Page 467: Mpu Error Address Register, Mpu Port 0 To 3 (Mpu_Earn)
MPU_CESR[SPERR] field set. Information on the faulting address is captured in the corresponding MPU_EARn register at the same time. A read of the MPU_EDRn register clears the corresponding bit in the MPU_CESR[SPERR] field. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 16-7...
Page 468: Mpu Region Descriptor N (Mpu_Rgdn)
The descriptor definition is fundamental to the operation of the MPU. The region descriptors are organized sequentially in the MPU’s programming model and each of the four 32-bit words are detailed in the subsequent sections. PXR40 Microcontroller Reference Manual, Rev. 1 16-8 Freescale Semiconductor...
Page 469 The corresponding access control is a 6-bit field defining separate privilege rights for user and supervisor mode accesses as well as the optional inclusion of a process PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 16-9...
Page 470 M6RE M6WE M5RE M5WE M4RE M4WE Reset (n=0) Reset (n>0) M0UM M0PE M0SM Reset (n=0) Reset (n>0) Note: Refer to Table 16-1to see the Master ID assignments. Figure 16-7. MPU Region Descriptor, Word 2 Register (MPU_RGDn.Word2) PXR40 Microcontroller Reference Manual, Rev. 1 16-10 Freescale Semiconductor...
Page 471 {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. Note: See Table 16-1 for the MPU Master ID list. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 16-11...
Page 472 Valid. This bit signals the region descriptor is valid. Any write to MPU_RGDn.Word{0,1,2} clears this bit, but a write to MPU_RGDn.Word3 sets or clears this bit depending on bit 31 of the write operand. 0 Region descriptor is invalid 1 Region descriptor is valid PXR40 Microcontroller Reference Manual, Rev. 1 16-12 Freescale Semiconductor...
Page 473: Mpu Region Descriptor Alternate Access Control N (Mpu_Rgdaacn)
Bus Master n Write Enable. If set, this flag allows bus master n to perform write operations. If cleared, any attempted write by bus master n terminates with an access error and the write is not performed. Note: See Table 16-1 for the MPU Master ID list. MnWE 8–25 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 16-13...
Page 474: Functional Description
Using the AHB supervisor/user mode signals, a set of permissions is generated from the appropriate fields in the region descriptor. The protection violation logic evaluates the access against the effective permissions. PXR40 Microcontroller Reference Manual, Rev. 1 16-14 Freescale Semiconductor...
Page 475: Ahb Error Terminations
When a new descriptor is loaded into a RGDn, it would typically be performed using four 32-bit word writes. As discussed in Section 16.2.2.4.4, MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3), the hardware assists in the maintenance of the valid PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 16-15...
Page 476 CP0 Code Flash CP1 Code CP0 Data & Stack CP0 -> CP1 Shared Data CP1 -> CP0 Shared Data CP0 Data & Stack Shared DMA Data Figure 16-10. Overlapping Region Descriptor Example PXR40 Microcontroller Reference Manual, Rev. 1 16-16 Freescale Semiconductor...
Page 477 (RGD7) accessible to both processors and the traditional eDMA master. This example is intended to show one possible application of the capabilities of the memory protection unit in a typical system. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 16-17...
Page 478 Memory Protection Unit (MPU) PXR40 Microcontroller Reference Manual, Rev. 1 16-18 Freescale Semiconductor...
Page 479: Introduction
To use ECC with SRAM, the SRAM memory must be written to before ECC is enabled. 17.1.1 Features The ECSM has this major feature: • Registers for capturing information on memory errors if error-correcting codes (ECC) are implemented. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 17-1...
Page 480: Memory Map And Registers
ECSM_REAT—RAM ECC attributes register 17.2.2.15/17-15 0x0068 ECSM_REDRH—RAM ECC data register high 17.2.2.16/17-16 0x006C ECSM_REDRL—RAM ECC data register low 17.2.2.16/17-16 0x0007–0x3FFF Reserved Please refer to the register definition. U = undefined at reset. PXR40 Microcontroller Reference Manual, Rev. 1 17-2 Freescale Semiconductor...
Page 481: Register Descriptions
Attempted writes of a different size than the register width produce an error termination of the bus cycle and no change to the targeted register. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 17-3...
Page 482: Processor Core Type (Ecsm_Pct)
1 Last recorded event was caused by a power-on reset (based on a device input signal) Device-input Reset 1 Last recorded event was a reset caused by a device input reset. PXR40 Microcontroller Reference Manual, Rev. 1 17-4 Freescale Semiconductor...
Page 483: Ecc Configuration Register (Ecsm_Ecr)
The occurrence of a single-bit flash correction generates a MCM ECC interrupt request as signalled by the assertion of ECSM_ESR[F1BC]. The address, attributes and data are also captured in the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers. 4–5 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 17-5...
Page 484: Ecc Status Register (Ecsm_Esr)
4. When the values are identical, write a 1 to the asserted ECSM_ESR flag to negate the interrupt request. Figure 17-3 Table 17-5 for the ECC status register definition. Offset: ECSM_BASE_ADDR + 0x0047 Access: User read/write R1BC F1BC RNCE FNCE Reset Figure 17-3. ECC Status (ECSM_ESR) Register PXR40 Microcontroller Reference Manual, Rev. 1 17-6 Freescale Semiconductor...
Page 485: Ecc Error Generation Register (Ecsm_Eegr)
The intent is to generate errors during data write cycles, such that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections or double-bit noncorrectable errors that are terminated with an error response. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 17-7...
Page 486 ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM. 0 No RAM continuous 2-bit data inversions are generated. 1 2-bit data inversions in the RAM are continuously generated. PXR40 Microcontroller Reference Manual, Rev. 1 17-8 Freescale Semiconductor...
Page 487: Flash Ecc Address Register (Ecsm_Fear)
ECSM_FEAR, ECSM_FEMR, ECSM_FEAT, and ECSM_FEDR registers and also the appropriate flag (F1BC or FNCE) in the ECC status register to be asserted. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 17-9...
Page 488: Flash Ecc Master Number Register (Ecsm_Femr)
Table 17-8. ECSM_FEMR Field Descriptions Field Description 0–7 Flash CC Master Number Register. Contains the XBAR bus master number of the faulting access of the last, FEMR properly enabled flash ECC event. PXR40 Microcontroller Reference Manual, Rev. 1 17-10 Freescale Semiconductor...
Page 489: Flash Ecc Attributes Register (Ecsm_Feat)
ECSM_FEAR, ECSM_FEMR, ECSM_FEAT, and ECSM_FEDR registers and also the appropriate flag (F1BC or FNCE) in the ECC status register to be asserted. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 17-11...
Page 490: Ram Ecc Address Register (Ecsm_Rear)
ECSM_RESR, ECSM_REMR, ECSM_REAT, and ECSM_REDR registers and also the appropriate flag (RNCE) in the ECC status register to be asserted. This register is read-only; any attempted write is ignored. See Figure 17-10 Table 17-11 for the RAM ECC address register definition. PXR40 Microcontroller Reference Manual, Rev. 1 17-12 Freescale Semiconductor...
Page 491: Ram Ecc Syndrome Register (Ecsm_Resr)
Figure 17-11 Table 17-12 for the RAM ECC syndrome register definition. Offset: ECSM_BASE_ADDR + 0x0065 Access: User read-only RESR[0:7] Reset Figure 17-11. RAM ECC Syndrome (ECSM_RESR) Register U = undefined at reset PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 17-13...
Page 492 DATA[51] 0xEA DATA[28] 0x2C DATA[13] 0x97 DATA[52] 0xEC DATA[29] 0x31 DATA[14] 0x98 DATA[53] 0xF1 DATA[30] 0x34 DATA[15] 0x9B DATA[54] 0xF4 DATA[31] 0x40 ECC[6] 0x9D DATA[55] Others Multiple 0x4A DATA[33] 0xA2 DATA[40] PXR40 Microcontroller Reference Manual, Rev. 1 17-14 Freescale Semiconductor...
Page 493: Ram Ecc Master Number Register (Ecsm_Remr)
Table 17-15 for the RAM ECC attributes register definition. Offset: ECSM_BASE_ADDR + 0x0067 Access: User read-only WRITE SIZE PROTECTION Reset Figure 17-13. RAM ECC Attributes (ECSM_REAT) Register U = undefined at reset PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 17-15...
Page 494: Ram Ecc Data Register (Ecsm_Redr)
RAM ECC data register definition. Offset: ECSM_BASE_ADDR + 0x0068 Access: User read-only REDR[0:15] Reset REDR[16:31] Reset Figure 17-14. RAM ECC Data High (ECSM_REDRH) Register U = undefined at reset PXR40 Microcontroller Reference Manual, Rev. 1 17-16 Freescale Semiconductor...
Page 495 RAM ECC Data Register. Contains the data associated with the faulting access of the last properly enabled platform REDR RAM ECC event. The register contains the data value taken directly from the platform data bus. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 17-17...
Page 496 Error Correction Status Module (ECSM) PXR40 Microcontroller Reference Manual, Rev. 1 17-18 Freescale Semiconductor...
Page 497: Introduction
In debug mode, operation of the counter is controlled by the FRZ bit in the SWT_MCR. If the FRZ bit is set, the counter is stopped in debug mode, otherwise it PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 18-1...
Page 498: External Signal Description
The following sections detail the individual registers within the SWT programming model. 18.3.2.1 SWT Control Register (SWT_MCR) The SWT_MCR contains fields for configuring and controlling the SWT. This register is read only if either the SWT_MCR[HLK] or SWT_MCR[SLK] bits are set. PXR40 Microcontroller Reference Manual, Rev. 1 18-2 Freescale Semiconductor...
Page 499 Soft Lock. This bit is cleared by writing the unlock sequence to the service register. 0 = SWT_MCR, SWT_TO, SWT_WN and SWT_SK are read/write registers if HLK=0 1 = SWT_MCR, SWT_TO, SWT_WN and SWT_SK are read only registers PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 18-3...
Page 500 0 = SWT counter continues to run in debug mode 1 = SWT counter is stopped in debug mode Watchdog Enabled. 0 = SWT is disabled 1 = SWT is enabled PXR40 Microcontroller Reference Manual, Rev. 1 18-4 Freescale Semiconductor...
Page 501: Swt Interrupt Register (Swt_Ir)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 1 1 0 1 0 0 0 0 Figure 18-3. SWT Time-Out Register (SWT_TO) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 18-5...
Page 502: Swt Window Register (Swt_Wn)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18-5. SWT Service Register (SWT_SR) PXR40 Microcontroller Reference Manual, Rev. 1 18-6 Freescale Semiconductor...
Page 503: Swt Counter Output Register (Swt_Co)
Therefore, the value read from this field immediately after disabling the watchdog may be higher than the actual value of the internal counter. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 18-7...
Page 504: Swt Service Key Register (Swt_Sk)
Service Key. This field is the previous (or initial) service key value used in keyed service mode. If SWT_MCR[KEY] is set, the next key value to be written to the SWT_SR is (17*SK+3) mod 2 PXR40 Microcontroller Reference Manual, Rev. 1 18-8 Freescale Semiconductor...
Page 505: Functional Description
However, due to synchronization logic in the SWT design, recognition of the service sequence or configuration changes may require up to three system plus seven counter clock cycles. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 18-9...
Page 506 Then the SWT can be disabled (SWT_MCR[WEN] cleared) and the value of the SWT_CO read to determine if the internal down counter is working properly. PXR40 Microcontroller Reference Manual, Rev. 1 18-10 Freescale Semiconductor...
Page 507: Introduction
The STM programming model has fourteen 32-bit registers. The STM registers can only be accessed using 32-bit (word) accesses. Attempted references using a different size or to a reserved address generates a bus error termination. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 19-1...
Page 508: Memory Map
0x0000_0000 19.3.2.5/5 0x003C Reserved 0x0040 STM_CCR3—STM Channel 3 Control Register 0x0000_0000 19.3.2.3/4 0x0044 STM_CIR3—STM Channel 3 Interrupt Register 0x0000_0000 19.3.2.4/5 0x0048 STM_CMP3—STM Channel 3 Compare Register 0x0000_0000 19.3.2.5/5 0x004C -0x3FFF Reserved PXR40 Microcontroller Reference Manual, Rev. 1 19-2 Freescale Semiconductor...
Page 509: Register Descriptions
0 = STM counter continues to run in debug mode. 1 = STM counter is stopped in debug mode. Timer Counter Enabled. 0 = Counter is disabled. 1 = Counter is enabled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 19-3...
Page 510: Stm Count Register (Stm_Cnt)
Reset Figure 19-3. STM Channel Control Register (STM_CCRn) Table 19-4. STM_CCRn Field Descriptions Field Description 0–30 Reserved Channel Enable. 0 = The channel is disabled. 1 = The channel is enabled. PXR40 Microcontroller Reference Manual, Rev. 1 19-4 Freescale Semiconductor...
Page 511: Stm Channel Interrupt Register (Stm_Cirn)
Compare value for channel n. If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the STM_CNT register, a channel interrupt request is generated and the STM_CIRn[CIF] bit is set. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 19-5...
Page 512: Functional Description
STM_CIR[CIF] bit and generate an interrupt request when the channel compare register matches the timer counter. The interrupt request is cleared by writing a 1 to the STM_CIRn[CIF] bit. A write of 0 to the STM_CIRn[CIF] bit has no effect. PXR40 Microcontroller Reference Manual, Rev. 1 19-6 Freescale Semiconductor...
Page 513: Introduction
It also provides a dedicated Real Time Interrupt Timer (RTI), which runs on a separate clock and can be used for system wakeup from low power mode. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 20-1...
Page 514: Block Diagram
RTI can be used to generate a CPU wake-up interrupt • RTI clock source is the crystal oscillator, no pre-scalars are used • PIT timer clock source is the peripheral clock, no pre-scalars are used PXR40 Microcontroller Reference Manual, Rev. 1 20-2 Freescale Semiconductor...
Page 515: Signal Description
PIT_CH2_LDVAL—Channel 2 load value register 0x0000_0000 20.3.2.2/5 0x124 PIT_CH2_CVAL—Channel 2 current value 0x0000_0000 20.3.2.3/5 register 0x128 PIT_CH2_TCTRL—Channel 2 timer control 0x0000_0000 20.3.2.4/5 register 0x12C PIT_CH2_TFLAG—Channel 2 timer channel flag 0x0000_0000 20.3.2.5/6 register PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 20-3...
Page 516: Register Descriptions
Reserved Freeze. Allows the timers to be stopped when the device enters debug mode. 0 = Timers continue to run in debug mode. 1 = Timers are stopped in debug mode. PXR40 Microcontroller Reference Manual, Rev. 1 20-4 Freescale Semiconductor...
Page 517: Timer Load Value Register (Pit_Rti_Ldval, Pit_Chn_Ldval)
NOTE: The timer values are frozen in Debug mode if the FRZ bit is set in the PIT Module Control Register (see Figure 20-2) 20.3.2.4 Timer Control Register (PIT_RTI_TCTRL, PIT_CHn_TCTRL) This register contains the control bits for each timer. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 20-5...
Page 518: Timer Flag Register (Pit_Rti_Tflg, Pit_Chn_Tflg)
To avoid this, the associated TIF flag must be cleared first. Timer Enable Bit. 0 Timer is disabled 1 Timer is active 20.3.2.5 Timer Flag Register (PIT_RTI_TFLG, PIT_CHn_TFLG) This register holds the PIT interrupt flag for each timer. PXR40 Microcontroller Reference Manual, Rev. 1 20-6 Freescale Semiconductor...
Page 519: Functional Description
All interrupts can be enabled or masked (by setting the TIE bits in the TCTRL registers). A new interrupt can be generated only after the previous one is cleared. If desired, the current counter value of the timer can be read via the CVAL registers. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 20-7...
Page 520: Debug Mode
In debug mode the timers may be configured to stop when the debugger halts the device. This is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system (e.g. the timer values) and then continue the operation. PXR40 Microcontroller Reference Manual, Rev. 1 20-8 Freescale Semiconductor...
Page 521: Interrupts
Low Power Mode – Using the RTI for System Wakeup This section describes the use of the low power mode, both with and without use of the RTI timer for wakeup. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 20-9...
Page 522: Low Power Mode Without Rti Wakeup
5. The CPU executes the ‘msync’, ‘isync’, and ‘wait’ instructions and the device enters low power mode. Note that the ‘msync’ and ‘isync’ instructions ensure that all current core operations complete before entering low power mode. PXR40 Microcontroller Reference Manual, Rev. 1 20-10 Freescale Semiconductor...
Page 523 However, the CPU will also exit low power mode under any of the following conditions: • Any external interrupt from interrupt controller • Critical interrupt • NMI event • Core watchdog timeout • Core fixed interval timeout • Core decrementer timeout • Various debug events PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 20-11...
Page 524 Periodic Interrupt Timer (PIT_RTI) PXR40 Microcontroller Reference Manual, Rev. 1 20-12 Freescale Semiconductor...
Page 525: Introduction
The hardware microarchitecture includes a DMA engine that performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-1...
Page 526: Block Diagram
— Connections to the crossbar switch for bus mastering the data movement • Transfer control descriptor organized to support two-deep, nested transfer operations — An inner data transfer loop defined by a minor byte transfer count PXR40 Microcontroller Reference Manual, Rev. 1 21-2 Freescale Semiconductor...
Page 527: Modes Of Operation
If the signal is asserted during transfer of a block of data described by a minor loop in the current active channel’s TCD, the eDMA continues operation until completion of the minor loop. 21.2 External Signal Description The eDMA has no external signals.. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-3...
Page 528: Memory Map And Registers
EDMA_x_SEEIR—eDMA set enable error interrupt register 0x00 21.3.2.7/21-25 0x001B EDMA_x_CEEIR—eDMA clear enable error interrupt register 0x00 21.3.2.8/21-26 0x001C EDMA_x_CIRQR—eDMA clear interrupt request register 0x00 21.3.2.9/21-27 0x001D EDMA_x_CER—eDMA clear error register 0x00 21.3.2.10/21-27 PXR40 Microcontroller Reference Manual, Rev. 1 21-4 Freescale Semiconductor...
Page 529 EDMA_x_CPR12—eDMA channel 12 priority register 0x0C 21.3.2.17/21-33 0x010D EDMA_x_CPR13—eDMA channel 13 priority register 0x0D 21.3.2.17/21-33 0x010E EDMA_x_CPR14—eDMA channel 14 priority register 0x0E 21.3.2.17/21-33 0x010F EDMA_x_CPR15—eDMA channel 15 priority register 0x0F 21.3.2.17/21-33 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-5...
Page 530 EDMA_A_CPR44—eDMA channel 44 priority register 0x2C 21.3.2.17/21-33 0x012D EDMA_A_CPR45—eDMA channel 45 priority register 0x2D 21.3.2.17/21-33 0x012E EDMA_A_CPR46—eDMA channel 46 priority register 0x2E 21.3.2.17/21-33 0x012F EDMA_A_CPR47—eDMA channel 47 priority register 0x2F 21.3.2.17/21-33 PXR40 Microcontroller Reference Manual, Rev. 1 21-6 Freescale Semiconductor...
Page 531 EDMA_x_TCD11—eDMA transfer control descriptor 11 — 21.3.2.18/21-34 0x1180 EDMA_x_TCD12—eDMA transfer control descriptor 12 — 21.3.2.18/21-34 0x11A0 EDMA_x_TCD13—eDMA transfer control descriptor 13 — 21.3.2.18/21-34 0x11C0 EDMA_x_TCD14—eDMA transfer control descriptor 14 — 21.3.2.18/21-34 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-7...
Page 532 EDMA_A_TCD43—eDMA transfer control descriptor 43 — 21.3.2.18/21-34 0x1580 EDMA_A_TCD44—eDMA transfer control descriptor 44 — 21.3.2.18/21-34 0x15A0 EDMA_A_TCD45—eDMA transfer control descriptor 45 — 21.3.2.18/21-34 0x15C0 EDMA_A_TCD46—eDMA transfer control descriptor 46 — 21.3.2.18/21-34 PXR40 Microcontroller Reference Manual, Rev. 1 21-8 Freescale Semiconductor...
Page 533 Request Interrupt Error Interrupt (EDMA_A_SERQR) (EDMA_A_CERQR) (EDMA_A_SEEIR) (EDMA_A_CEEIR) 0xFFF4_401C eDMA Clear Interrupt eDMA Clear eDMA Set Start Bit, eDMA Clear Done Request Error Activate Channel Status Bit (EDMA_A_CIRQR) (EDMA_A_CER) (EDMA_A_SSBR) (EDMA_A_CDSBR) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-9...
Page 534 Channel 31 Priority Priority Priority Priority (EDMA_A_CPR28) (EDMA_A_CPR29) (EDMA_A_CPR30) (EDMA_A_CPR31) 0xFFF4_4120 eDMA Channel 32 eDMA Channel 33 eDMA Channel 34 eDMA Channel 35 Priority Priority Priority Priority (EDMA_A_CPR32) (EDMA_A_CPR33) (EDMA_A_CPR34) (EDMA_A_CPR35) PXR40 Microcontroller Reference Manual, Rev. 1 21-10 Freescale Semiconductor...
Page 535 Table 21-3. eDMA_B 32-bit Memory Map—Graphical View Address Register 0xFFF5_4000 eDMA Control Register (EDMA_B_CR) 0xFFF5_4004 eDMA Error Status (EDMA_B_ESR) 0xFFF5_4008 Reserved 0xFFF5_400C eDMA Enable Request eDMA Enable Request (EDMA_B_ERQRL, channels 31–16) (EDMA_B_ERQRL, channels 15–00) 0xFFF5_4010 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-11...
Page 536 Channel 23 Priority Priority Priority Priority (EDMA_B_CPR20) (EDMA_B_CPR21) (EDMA_B_CPR22) (EDMA_B_CPR23) 0xFFF5_4118 eDMA Channel 24 eDMA Channel 25 eDMA Channel 26 eDMA Channel 27 Priority Priority Priority Priority (EDMA_B_CPR24) (EDMA_B_CPR25) (EDMA_B_CPR26) (EDMA_B_CPR27) PXR40 Microcontroller Reference Manual, Rev. 1 21-12 Freescale Semiconductor...
Page 537: Register Descriptions
Arbitration within a group can be configured to use a fixed priority or a round robin. In fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The priorities are PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-13...
Page 538 When minor loop mapping is disabled (EDMA_x_MCR[EMLM] = 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. See Section 21.3.2.18, Transfer Control Descriptor (TCD), for more details. PXR40 Microcontroller Reference Manual, Rev. 1 21-14 Freescale Semiconductor...
Page 539 ECX treats the cancel as an error condition; thus updating the EDMA_x_ESR register and generating an optional error interrupt. See Section 21.3.2.2, eDMA Error Status Register (EDMA_x_ESR). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-15...
Page 540 1 The assertion of the system debug control input causes the eDMA to stall the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when either the system debug control input is negated or the EDBG bit is cleared. Reserved PXR40 Microcontroller Reference Manual, Rev. 1 21-16 Freescale Semiconductor...
Page 541: Edma Error Status Register (Edma_X_Esr)
EDMA_x_ESR[ERRCHN] field and the EDMA_x_ESR[ECX] and EDMA_x_ESR[VLD] bits are set. In addition, an error interrupt may be generated if enabled. Refer to Section 21.3.2.14, eDMA Error Registers (EDMA_x_ERH, EDMA_x_ERL). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-17...
Page 542 Note: Do not rely on the number in the ERRCHN field group for channel-priority errors. Group- and Channel-priority errors must be resolved by inspection. The application code must interrogate the priority registers to find groups or channels with duplicate priority level. PXR40 Microcontroller Reference Manual, Rev. 1 21-18 Freescale Semiconductor...
Page 543: Edma Enable Request Registers (Edma_A_Erqrh, Edma_X_Erqrl)
The EDMA_A_ERQRH and EDMA_x_ERQRL provide a bit map for the 32 (or 64 for eDMA_A) channels to enable the request signal for each channel. EDMA_A_ERQRH supports channels 63–32, while EDMA_x_ERQRL covers channels 31–0. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-19...
Page 544 As a given channel completes processing its major iteration count, there is a flag in the transfer control descriptor that may affect the ending state of the EDMA_x_ERQR bit for that channel. If the PXR40 Microcontroller Reference Manual, Rev. 1 21-20 Freescale Semiconductor...
Page 545: Edma Enable Error Interrupt Registers (Edma_A_Eeirh, Edma_X_Eeirl)
Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted. Address: EDMA_A_BASE + 0x0010 Access: User read/write R EEI Reset R EEI Reset Figure 21-7. eDMA Enable Error Interrupt High Register (EDMA_A_EEIRH) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-21...
Page 546 Enable Error Interrupt n. EEIn 0 The error signal for channel n does not generate an error interrupt. 1 The assertion of the error signal for channel n generate an error interrupt request. PXR40 Microcontroller Reference Manual, Rev. 1 21-22 Freescale Semiconductor...
Page 547: Edma Set Enable Request Register (Edma_X_Serqr)
Set Enable Request. SERQ 0–31 (63 for eDMA_A) Set corresponding bit in EDMA_A_ERQRH or EDMA_x_ERQRL. 64–127 Set all bits in EDMA_A_ERQRH and EDMA_x_ERQRL. Bit 2 (SERQR[1]) is not used on eDMA_B. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-23...
Page 548: Edma Clear Enable Request Register (Edma_X_Cerqr)
Clear Enable Request. CERQ 0–31 (63 for eDMA_A) Clear corresponding bit in EDMA_A_ERQRH or EDMA_x_ERQRL. 64–127 Clear all bits in EDMA_A_ERQRH and EDMA_x_ERQRL. Bit 2 (CERQR[1]) is not used on eDMA_B. PXR40 Microcontroller Reference Manual, Rev. 1 21-24 Freescale Semiconductor...
Page 549: Edma Set Enable Error Interrupt Register (Edma_X_Seeir)
Set Enable Error Interrupt. SEEI[0:6] 0–31 (63 for eDMA_A) Set corresponding bit in EDMA_A_EIRRH or EDMA_x_EIRRL. 64–127 Set all bits in EDMA_A_EIRRH or EDMA_x_EEIRL. Bit 2(SEEIR[1]) is not used on eDMA_B. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-25...
Page 550: Edma Clear Enable Error Interrupt Register (Edma_X_Ceeir)
Clear Enable Error Interrupt. CEEI 0–31 (63 for eDMA_A) Clear corresponding bit in EDMA_A_EEIRH or EDMA_x_EEIRL. 64–127 Clear all bits in EDMA_A_EEIRH or EDMA_x_EEIRL. Bit 2 (CEEIR[1]) is not used on eDMA_B. PXR40 Microcontroller Reference Manual, Rev. 1 21-26 Freescale Semiconductor...
Page 551: Edma Clear Interrupt Request Register (Edma_X_Cirqr)
EDMA_x_ERL to be zeroed, clearing all channel error indicators. Reads of this register return all zeroes. If bit 0 is set, the CERR command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-27...
Page 552: Edma Set Start Bit Register (Edma_X_Ssbr)
If bit 0 is set, the SSB command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes. Offset: EDMA_x_BASE + 0x001E Access: User write-only W NOP SSB[0:6] Reset Figure 21-15. eDMA Set START Bit Register (EDMA_x_SSBR) PXR40 Microcontroller Reference Manual, Rev. 1 21-28 Freescale Semiconductor...
Page 553: Edma Clear Done Status Bit Register (Edma_X_Cdsbr)
1 No operation, ignore bits 1–7. 1–7 Clear DONE Status Bit. CDSB 0–31 (63 for eDMA_A) Clear the corresponding channel’s DONE bit. 64–127 Clear all TCD DONE bits. Bit 2 (CDSBR[1]) is not used on eDMA_B. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-29...
Page 554: Edma Interrupt Request Registers (Edma_A_Irqrh, Edma_X_Irqrl)
R INT Reset Figure 21-17. eDMA Interrupt Request High Register (EDMA_A_IRQRH) Address: EDMA_x_BASE + 0x0024 Access: User read/write R INT Reset R INT Reset Figure 21-18. eDMA Interrupt Request Register (EDMA_x_IRQRL) PXR40 Microcontroller Reference Manual, Rev. 1 21-30 Freescale Semiconductor...
Page 555: Edma Error Registers (Edma_X_Erh, Edma_X_Erl)
EDMA_x_CER is provided so the error indicator for a single channel can be cleared. Address: EDMA_A_BASE + 0x0028 Access: User R/W R ERR Reset R ERR Reset Figure 21-19. eDMA Error High Register (EDMA_A_ERH) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-31...
Page 556: Dma Hardware Request Status (Edma_A_Hrsh, Edma_X_Hrsl)
64–32 and EDMA_x_HRSL maps to channels 31-00. Address: EDMA_A_BASE + 0x0030 Access: User R/W R HRS Reset R HRS Reset Figure 21-21. EDMA Hardware Request Status Register High (EDMA_A_HRSH) PXR40 Microcontroller Reference Manual, Rev. 1 21-32 Freescale Semiconductor...
Page 557: Edma Global Write Registers (Edma_X_Gwrh And Edma_X_Gwrl)
Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of starting a higher priority channel. After the preempting channel has completed all its minor loop PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-33...
Page 558: Transfer Control Descriptor (Tcd)
21.3.2.18 Transfer Control Descriptor (TCD) Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel PXR40 Microcontroller Reference Manual, Rev. 1 21-34 Freescale Semiconductor...
Page 559 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Figure 21-24. TCD Structure The fields implemented in Word 2 depend on whether EDMA_x_MCR(EMLM) is set to 0 or 1. Refer to Table 21-4. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-35...
Page 560 This flag selects whether the minor loop offset is applied to the source address upon minor SMLOE loop completion. 0 The minor loop offset is not applied to the saddr. 1 The minor loop offset is applied to the saddr. PXR40 Microcontroller Reference Manual, Rev. 1 21-36 Freescale Semiconductor...
Page 561 TCD bits [161:175] are used to form a 15-bit CITER field. CITER.LINKCH Otherwise, • After the minor loop is exhausted, the DMA engine initiates a channel service request at the channel defined by CITER.LINKCH[0:5] by setting that channel’s EDMA_x_TCD.START bit. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-37...
Page 562 Note: When the TCD is first loaded by software, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. PXR40 Microcontroller Reference Manual, Rev. 1 21-38 Freescale Semiconductor...
Page 563 1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA field provides a memory pointer to the next TCD to be loaded into this channel after the outer major loop completes its execution. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-39...
Page 564: Functional Description
— When another channel is activated, the contents of its transfer control descriptor is read from the local memory and loaded into the registers of the other address path channel{x,y}. After the inner minor loop completes execution, the address path hardware writes the new values for PXR40 Microcontroller Reference Manual, Rev. 1 21-40 Freescale Semiconductor...
Page 565 DMA engine is given priority and the slave transaction is stalled. — Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM memory array. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-41...
Page 566: Edma Basic Data Flow
(address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. The source reads are initiated and the fetched data is PXR40 Microcontroller Reference Manual, Rev. 1 21-42 Freescale Semiconductor...
Page 567 TCD from memory using the scatter-gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 21-27. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-43...
Page 568: Initialization / Application Information
5. Enable any hardware service requests via the EDMA_x_ERQRH and/or EDMA_x_ERQRL registers. 6. Request channel service by software (setting the EDMA_x_TCD.START bit) or by hardware (slave device asserting its DMA peripheral request signal). PXR40 Microcontroller Reference Manual, Rev. 1 21-44 Freescale Semiconductor...
Page 569 DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (biter). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-45...
Page 570 • after major loop • Peripheral queues typically Last minor loop (typically used to • have size and offset loop back) equal to NBYTES Figure 21-29. Memory Array Terms PXR40 Microcontroller Reference Manual, Rev. 1 21-46 Freescale Semiconductor...
Page 571: Dma Programming Errors
(channel/group) with that priority is selected by arbitration and executed by the DMA engine. The hardware service request handshake signals, error interrupts, and error reporting are associated with the selected channel. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-47...
Page 572: Dma Request Assignments
EMIOS.GFR[F0] eMIOS channel 0 Flag eMIOS_GFR_F1 EMIOS.GFR[F1] eMIOS channel 1 Flag eMIOS_GFR_F2 EMIOS.GFR[F2] eMIOS channel 2 Flag eMIOS_GFR_F3 EMIOS.GFR[F3] eMIOS channel 3 Flag eMIOS_GFR_F4 EMIOS.GFR[F4] eMIOS channel 4 Flag PXR40 Microcontroller Reference Manual, Rev. 1 21-48 Freescale Semiconductor...
Page 573 SIU External Interrupt Flag 3 eTPU_CDTRSR_B_DTRS0 ETPU.CDTRSR_B[DTRS0] eTPUB Channel 0 Data Transfer Request Status eTPU_CDTRSR_B_DTRS1 ETPU.CDTRSR_B[DTRS1] eTPUB Channel 1 Data Transfer Request Status eTPU_CDTRSR_B_DTRS2 ETPU.CDTRSR_B[DTRS2] eTPUB Channel 2 Data Transfer Request Status PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-49...
Page 574 Decimation Filter C Output Buffer Drain Flag DECFILTERD_IB DECFILTERD.IB Decimation Filter D Input Buffer Fill Flag DECFILTERD_OB DECFILTERD.OB Decimation Filter D Output Buffer Drain Flag DECFILTERE_IB DECFILTERE.IB Decimation Filter E Input Buffer Fill Flag PXR40 Microcontroller Reference Manual, Rev. 1 21-50 Freescale Semiconductor...
Page 575 DECFILTERG.OB Decimation Filter G Output Buffer Drain Flag DECFILTERH_IB DECFILTERH.IB Decimation Filter H Input Buffer Fill Flag DECFILTERH_OB DECFILTERH.OB Decimation Filter H Output Buffer Drain Flag No Request 28–31 — — PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-51...
Page 576: Dma Arbitration Mode Considerations
This scenario ensures that all channels are guaranteed service at some point, regardless of the request rates. However, the potential latency could be high. All channels are treated equally. Priority levels are not used in round-robin/round-robin mode. PXR40 Microcontroller Reference Manual, Rev. 1 21-52 Freescale Semiconductor...
Page 577: Fixed-Group Arbitration, Round-Robin Channel Arbitration
EDMA_x_TCD.START = 1 (Must be written last after all other fields have been initialized) All other TCD fields = 0 This would generate the following sequence of events: 1. Slave write to the EDMA_x_TCD.START bit requests channel service. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-53...
Page 578: Multiple Requests
EDMA_x_TCD.SLAST = –32 EDMA_x_TCD.DADDR = 0x2000 EDMA_x_TCD.DOFF = 4 EDMA_x_TCD.DSIZE = 2 EDMA_x_TCD.DLAST_SGA = –32 EDMA_x_TCD.INT_MAJ = 1 EDMA_x_TCD.START = 0 (Must be written last after all other fields have been initialized) PXR40 Microcontroller Reference Manual, Rev. 1 21-54 Freescale Semiconductor...
Page 579  last iteration of the minor loop  major loop complete 14. eDMA engine writes: EDMA_x_TCD.SADDR = 0x1000, EDMA_x_TCD.DADDR = 0x2000, EDMA_x_TCD.CITER = 2 (EDMA_x_TCD.BITER). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-55...
Page 580: Modulo Feature
The TCD status bits execute the following sequence for a software activated channel: 1. EDMA_x_TCD.START = 1, EDMA_x_TCD.ACTIVE = 0, EDMA_x_TCD.DONE = 0 (channel service request via software). PXR40 Microcontroller Reference Manual, Rev. 1 21-56 Freescale Semiconductor...
Page 581: Active Channel Tcd Reads
The EDMA_x_TCD.ACTIVE bit for the preempted channel remains asserted throughout the preemption. The preempted channel is temporarily suspended while the preempting channel executes one iteration of PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-57...
Page 582: Channel Linking
Table 21-26 summarizes how a DMA channel can link to another DMA channel, i.e, use another channel’s TCD, at the end of a loop. PXR40 Microcontroller Reference Manual, Rev. 1 21-58 Freescale Semiconductor...
Page 583: Dynamic Programming
TCD local memory controller forces the EDMA_x_TCD.MAJOR.E_LINK and EDMA_x_TCD.E_SG bits to zero on any writes to a channel’s TCD after that channel’s EDMA_x_TCD.DONE bit is set indicating the major loop is complete. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 21-59...
Page 584 Enhanced Direct Memory Access Controller (eDMA) NOTE The user must clear the EDMA_x_TCD.DONE bit before writing the EDMA_x_TCD.MAJOR.E_LINK or EDMA_x_TCD.E_SG bits. The EDMA_x_TCD.DONE bit is cleared automatically by the eDMA engine after a channel begins execution. PXR40 Microcontroller Reference Manual, Rev. 1 21-60 Freescale Semiconductor...
Page 585: Introduction
MBNum Message Buffer Number: Position of message buffer configuration registers within the register map. For example, Message Buffer Number 5 corresponds to the MBCCS5 register. Microcontroller Unit T Microtick Macrotick PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-1...
Page 586: Color Coding
The controller has three main components: • Controller host interface (CHI) • Protocol engine (PE) • Clock domain crossing unit (CDC) A block diagram of the controller with its surrounding modules is given in Figure 22-1. PXR40 Microcontroller Reference Manual, Rev. 1 22-2 Freescale Semiconductor...
Page 587 All flexray memory related offsets are stored in offset registers. The physical address pointer into the flexray memory window of the MCU system memory is calculated using the offset values the flexray memory base address. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-3...
Page 588: Features
— means provided to safely disable individual message buffers — disabled message buffers can be reconfigured • two independent receive FIFOs — one receive FIFO per channel — up to 255 entries for each FIFO PXR40 Microcontroller Reference Manual, Rev. 1 22-4 Freescale Semiconductor...
Page 589: Modes Of Operation
Normal Mode In this mode the controller is fully functional. The controller indicates that it is in Normal Mode by asserting the module enable bit MEN in the Module Configuration Register (MCR). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-5...
Page 590: External Signal Description
The FR_A_RX signal carries the receive data for channel A from the corresponding FlexRay bus driver. 22.2.1.2 FR_A_TX — Transmit Data Channel A The FR_A_TX signal carries the transmit data for channel A to the corresponding FlexRay bus driver. PXR40 Microcontroller Reference Manual, Rev. 1 22-6 Freescale Semiconductor...
Page 591: Fr_A_Tx_En — Transmit Enable Channel A
If the protocol engine is clocked by the internal crystal oscillator, an 40 MHz crystal or CMOS compatible clock must be connected to the oscillator pins. The crystal or clock must fulfill the requirements given by the FlexRay Communications System Protocol Specification, Version 2.1 Rev A. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-7...
Page 592: Pll Clocking
Channel A Status Error Counter Register (CASERCR) 0x0026 Channel B Status Error Counter Register (CBSERCR) Protocol Status 0x0028 Protocol Status Register 0 (PSR0) 0x002A Protocol Status Register 1 (PSR1) 0x002C Protocol Status Register 2 (PSR2) PXR40 Microcontroller Reference Manual, Rev. 1 22-8 Freescale Semiconductor...
Page 593 Slot Status Register 0 (SSR0) 0x006A Slot Status Register 1 (SSR1) 0x006C Slot Status Register 2 (SSR2) 0x006E Slot Status Register 3 (SSR3) 0x0070 Slot Status Register 4 (SSR4) 0x0072 Slot Status Register 5 (SSR5) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-9...
Page 594 Receive FIFO System Memory Base Address Low Register (RFSYMBADLR) 0x00EC Receive FIFO Periodic Timer Register (RFPTR) Receive FIFO - Control (cont.) 0x00EE Receive FIFO Fill Level and POP Count Register (RFFLPCR) PXR40 Microcontroller Reference Manual, Rev. 1 22-10 Freescale Semiconductor...
Page 595: Register Descriptions
The registers mentioned above are located in physical memory blocks and, thus, they are not affected by reset. For some register fields, additional reset conditions exist. These additional PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-11...
Page 596: Register Write Access
The following memory mapped registers are used to access multiple internal registers. • Strobe Signal Control Register (STBSCR) • Slot Status Selection Register (SSSR) • Slot Status Counter Condition Register (SSCCR) • Receive Shadow Buffer Index Register (RSBIR) PXR40 Microcontroller Reference Manual, Rev. 1 22-12 Freescale Semiconductor...
Page 597: Module Version Register (Mvr)
Write: MEN, SBFF, SCM, CHB, CHA, FUM, FAM, CLKSEL, BITRATE: Disabled Mode SFFE: Disabled Mode or POC:config MEN SBFF SCM CHA SFFE BITRATE Reset Figure 22-3. Module Configuration Register (MCR) This register defines the global configuration of the controller. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-13...
Page 598 FlexRay Bus Bit Rate — This bit field defines the FlexRay Bus Bit Rate.00010.0 Mbit/sec 001 5.0 Mbit/sec 010 2.5 Mbit/sec 011 8.0 Mbit/sec 100 reserved 101 reserved 110 reserved 111 reserved PXR40 Microcontroller Reference Manual, Rev. 1 22-14 Freescale Semiconductor...
Page 599: System Memory Base Address Register (Symbadr)
The system memory base address registers define the base address of the flexray memory within the system memory. The base address is used by the BMIF to calculate the physical memory address for system memory accesses. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-15...
Page 600: Strobe Signal Control Register (Stbscr)
All strobe signals that are enabled and assigned to the same strobe port are combined with a binary OR operation. 00 assign selected signal to FR_DBG[0] 01 assign selected signal to FR_DBG[1] 10 assign selected signal to FR_DBG[2] 11 assign selected signal to FR_DBG[3] PXR40 Microcontroller Reference Manual, Rev. 1 22-16 Freescale Semiconductor...
Page 601: Message Buffer Data Size Register (Mbdsr)
MBSEG1DS Message Buffer Segment 1 Data Size — The field defines the size of the message buffer data section in two-byte entities for message buffers within the first message buffer segment. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-17...
Page 602: Message Buffer Segment Size And Utilization Register (Mbssutr)
Section 22.7.4, Protocol Control Command Execution. External clock correction commands are issued by writing to the EOC_AP and ERC_AP fields. For more information on external clock correction, refer to Section 22.6.11, External Clock Synchronization. PXR40 Microcontroller Reference Manual, Rev. 1 22-18 Freescale Semiconductor...
Page 603 1000 WAKEUP — Immediately initiate the wakeup procedure. 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved Delayed means on completion of current communication cycle. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-19...
Page 604: Global Interrupt Flag And Enable Register (Gifer)
FIFO B entries is at least 1 and the periodic timer as defined by Receive FIFO Periodic Timer Register (RFPTR) expires. 0 no such event 1 FIFO B almost full event has occurred PXR40 Microcontroller Reference Manual, Rev. 1 22-20 Freescale Semiconductor...
Page 605 Receive FIFO Channel A Almost Full Interrupt Enable — This flag controls if the FIFO A interrupt line is asserted when the FAFAIF flag is set. 0 Disable interrupt line 1 Enable interrupt line PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-21...
Page 606: Protocol Interrupt Flag Register 0 (Pifr0)
Protocol Operation Control Register (POCR). If the value of listen_timeout is equal to zero, the protocol configuration setting is considered as illegal. 0 No such event. 1 Illegal protocol configuration detected. PXR40 Microcontroller Reference Manual, Rev. 1 22-22 Freescale Semiconductor...
Page 607 B crosses the slot boundary. This is related to the transmission across slot boundary violation as described in the FSP process of the FlexRay protocol. 0 No such event. 1 Transmission across boundary violation occurred on channel B. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-23...
Page 608: Protocol Interrupt Flag Register 1 (Pifr1)
Protocol State Changed Interrupt Flag — This flag is set when the protocol state in the PROTSTATE field in Protocol Status Register 0 (PSR0) has changed. 0 No such event. 1 Protocol state changed. PXR40 Microcontroller Reference Manual, Rev. 1 22-24 Freescale Semiconductor...
Page 609: Protocol Interrupt Enable Register 0 (Pier0)
0 interrupt request generation disabled 1 interrupt request generation enabled MOC_IE Missing Offset Correction Interrupt Enable — This bit controls MOC_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-25...
Page 610: Protocol Interrupt Enable Register 1 (Pier1)
Figure 22-14. Protocol Interrupt Enable Register 1 (PIER1) This register defines whether or not the individual interrupt flags defined in Protocol Interrupt Flag Register 1 (PIFR1) can generate a protocol interrupt request. PXR40 Microcontroller Reference Manual, Rev. 1 22-26 Freescale Semiconductor...
Page 611: Chi Error Flag Register (Chierfr)
This register holds the CHI related error flags. The interrupt generation for each of these error flags is controlled by the CHI interrupt enable bit CHIE in the Global Interrupt Flag and Enable Register (GIFER). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-27...
Page 612 In this case, the controller does not grant the lock to the transmit side of a double transmit message buffer. 0 No such event 1 Double transmit buffer lock error occurred PXR40 Microcontroller Reference Manual, Rev. 1 22-28 Freescale Semiconductor...
Page 613: Message Buffer Interrupt Vector Register (Mbivec)
0 No such event 1 Illegal system bus address accessed 22.5.2.16 Message Buffer Interrupt Vector Register (MBIVEC) Base + 0x0022 TBIVEC RBIVEC Reset Figure 22-16. Message Buffer Interrupt Vector Register (MBIVEC) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-29...
Page 614: Channel A Status Error Counter Register (Casercr)
22.5.2.18 Channel B Status Error Counter Register (CBSERCR) Base + 0x0026 Additional Reset: RUN Command STATUS_ERR_CNT Reset Figure 22-18. Channel B Status Error Counter Register (CBSERCR) PXR40 Microcontroller Reference Manual, Rev. 1 22-30 Freescale Semiconductor...
Page 615: Protocol Status Register 0 (Psr0)
10 ALL 11 reserved PROTSTATE Protocol State — protocol related variable: vPOC!State. This field indicates the state of the protocol. POC:default config POC:config POC:wakeup POC:ready POC:normal passive POC:normal active POC:halt POC:startup PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-31...
Page 616: Protocol Status Register 1 (Psr1)
This indicates that this node has started the network 0 No such event POC:normal active reached from POC:startup state via leading cold start path PXR40 Microcontroller Reference Manual, Rev. 1 22-32 Freescale Semiconductor...
Page 617: Protocol Status Register 2 (Psr2)
The clock synchronization related CLKCORRFAILCNT is updated by the controller after the end of the static segment and before the end of the current communication cycle. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-33...
Page 618 This status bit is set if there was some media activity on the FlexRay bus channel A at the start or at the end of the symbol window. 0 No such event 1 Media activity at boundaries detected PXR40 Microcontroller Reference Manual, Rev. 1 22-34 Freescale Semiconductor...
Page 619: Protocol Status Register 3 (Psr3)
B in a slot that also contained an additional communication with either syntax error, content error, or boundary violations. 0 No additional communication detected 1 Additional communication detected PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-35...
Page 620: Macrotick Counter Register (Mtctr)
A. 0 No syntactically valid frames received 1 At least one syntactically valid frame received 22.5.2.23 Macrotick Counter Register (MTCTR) Base + 0x0030 MTCT Reset Figure 22-23. Macrotick Counter Register (MTCTR) PXR40 Microcontroller Reference Manual, Rev. 1 22-36 Freescale Semiconductor...
Page 621: Cycle Counter Register (Cyctr)
Field Description SLOTCNTA Slot Counter Value for Channel A — protocol related variable: vSlotCounter for channel A This field provides the number of the current slot in the current communication cycle. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-37...
Page 622: Slot Counter Channel B Register (Sltctbr)
Protocol Interrupt Flag Register 0 (PIFR0). Note: If the controller was not able to calculate a new rate correction term due to a lack of synchronization frames, the RATECORR value is not updated. PXR40 Microcontroller Reference Manual, Rev. 1 22-38 Freescale Semiconductor...
Page 623: Offset Correction Value Register (Ofcorvr)
Interrupt Flag and Enable Register (GIFER). NOTE The meanings of the combined status bits MIF, PRIF, CHIF, RBIF, and TBIF are different from those mentioned in the Global Interrupt Flag and Enable Register (GIFER). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-39...
Page 624: System Memory Access Time-Out Register (Symator)
System Memory Access Time-Out — This value defines the maximum amount of time to finish a system bus access in order to ensure correct frame transmission and reception (see Section 22.6.19.2, System Bus Access Timeout). PXR40 Microcontroller Reference Manual, Rev. 1 22-40 Freescale Semiconductor...
Page 625: Sync Frame Counter Register (Sfcntr)
Figure 22-32. Sync Frame Table Offset Register (SFTOR) This register defines the Flexray Memory related offset for sync frame tables. For more details, see Section 22.6.12, Sync Frame ID and Sync Frame Deviation Tables. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-41...
Page 626: Sync Frame Table Configuration, Control, Status Register (Sftccsr)
Tables for the odd cycle are valid. The controller clears this status bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 Tables are not valid (update is ongoing) 1 Tables are valid (consistent). PXR40 Microcontroller Reference Manual, Rev. 1 22-42 Freescale Semiconductor...
Page 627: Sync Frame Id Rejection Filter Register (Sfidrfr)
Sync Frame Rejection ID — This field defines the frame ID of a frame that must not be used for clock synchronization. For details see Section 22.6.15.2, Sync Frame Rejection Filtering. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-43...
Page 628: Sync Frame Id Acceptance Filter Value Register (Sfidafvr)
Base + 0x004C (NMVR0) Base + 0x004E (NMVR1) Base + 0x0050 (NMVR2) Base + 0x0052 (NMVR3) Base + 0x0054 (NMVR4) Base + 0x0056 (NMVR5) NMVP[15:8] NMVP[7:0] Reset Figure 22-37. Network Management Vector Registers (NMVR0–NMVR5) PXR40 Microcontroller Reference Manual, Rev. 1 22-44 Freescale Semiconductor...
Page 629: Network Management Vector Length Register (Nmvlr)
Field Description NMVL Network Management Vector Length — protocol related variable: gNetworkManagementVectorLength This field defines the length of the Network Management Vector in bytes. Legal values are between 0 and 12. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-45...
Page 630: Timer Configuration And Control Register (Ticcr)
Timer T1 State — This status bit provides the current state of timer T1. 0 timer T1 is idle 1 timer T1 is running NOTE Both timers are deactivated immediately when the protocol enters a state different from POC:normal active POC:normal passive. PXR40 Microcontroller Reference Manual, Rev. 1 22-46 Freescale Semiconductor...
Page 631: Timer 1 Cycle Set Register (Ti1Cysr)
T1_MTOFFSET Timer 1 Macrotick Offset — This field defines the macrotick offset value for timer 1. NOTE If the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer T1 will expire according to the changed value. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-47...
Page 632: Timer 2 Configuration Register 0 (Ti2Cr0)
22.5.2.43 Timer 2 Configuration Register 1 (TI2CR1) Base + 0x0062 Write: Anytime T2_MTOFFSET T2_MTCNT[15:0] Reset Figure 22-43. Timer 2 Configuration Register 1 (TI2CR1) PXR40 Microcontroller Reference Manual, Rev. 1 22-48 Freescale Semiconductor...
Page 633: Slot Status Selection Register (Sssr)
Write Mode — This control bit defines the write mode of this register. 0 Write to all fields in this register on write access. 1 Write to SEL field only on write access. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-49...
Page 634: Slot Status Counter Condition Register (Ssccr)
Slot Status Counter Registers (SSCR0–SSCR3). The correspondence is given in Table 22-54. For a detailed description of slot status counters, refer to Section 22.6.18.4, Slot Status Counter Registers. PXR40 Microcontroller Reference Manual, Rev. 1 22-50 Freescale Semiconductor...
Page 635 STATUSMASK[0] – This bit enables the counting for slots with the transmission conflict indicator bit set to 1. Table 22-54. Mapping between internal SSCCRn and SSCRn Condition Register Condition Defined for Register SSCCR0 SSCR0 SSCCR1 SSCR1 SSCCR2 SSCR2 SSCCR3 SSCR3 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-51...
Page 636: Slot Status Registers (Ssr0–Ssr7)
B vSS!ContentError vSS!ContentError Boundary Violation on Channel B — protocol related variable: vSS!BViolation channel B vSS!BViolation vSS!BViolation Transmission Conflict on Channel B — protocol related variable: vSS!TxConflict channel B vSS!TxConflict vSS!TxConflict PXR40 Microcontroller Reference Manual, Rev. 1 22-52 Freescale Semiconductor...
Page 637: Slot Status Counter Registers (Sscr0–Sscr3)
The provided value depends on the control bits and fields in the related internal slot status counter condition register SSCCRn, which can be programmed by using the Slot Status Counter Condition Register (SSCCR). For more details, see Section 22.6.18.4, Slot Status Counter Registers. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-53...
Page 638: Mts A Configuration Register (Mtsacfr)
Reset Figure 22-49. MTS B Configuration Register (MTSBCFR) This register controls the transmission of the Media Access Test Symbol MTS on channel B. For more details, see Section 22.6.13, MTS Generation. PXR40 Microcontroller Reference Manual, Rev. 1 22-54 Freescale Semiconductor...
Page 639: Receive Shadow Buffer Index Register (Rsbir)
Updates the message buffer header index after successful reception. Application: Provides initial message buffer header index. 22.5.2.51 Receive FIFO System Memory Base Address Register (RFSYMBADR) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-55...
Page 640: Receive Fifo Periodic Timer Register (Rfptr)
Periodic Timer Duration — This value defines the periodic timer duration in terms of macroticks. 0000 timer stays expired 3FFF timer never expires other timer expires after specified number of macroticks, expires and is restarted at each cycle start PXR40 Microcontroller Reference Manual, Rev. 1 22-56 Freescale Semiconductor...
Page 641: Receive Fifo Watermark And Selection Register (Rfwmsr)
Base + 0x0088 Write: POC:config SIDX /SIDX Reset Figure 22-55. Receive FIFO Start Index Register (RFSIR) This register defines the message buffer header index of the first message buffer of the selected FIFO. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-57...
Page 642: Receive Fifo Depth And Size Register (Rfdsr)
If the new style FIFO mode is configured (MCR.FIMD=1), the controller updates this index by PCA entries, when the application writes to the Receive FIFO Fill Level and POP Count Register (RFFLPCR). PXR40 Microcontroller Reference Manual, Rev. 1 22-58 Freescale Semiconductor...
Page 643: Receive Fifo B Read Index Register (Rfbrir)
Pop Count FIFO B — This field defines the number of entries to be removed from FIFO B. Pop Count FIFO A— This field defines the number of entries to be removed from FIFO A. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-59...
Page 644: Receive Fifo Message Id Acceptance Filter Value Register (Rfmidafvr)
ID filtering see Section 22.6.9.9, FIFO Filtering. Table 22-70. RFMIAFMR Field Descriptions Field Description MIDAFMSK Message ID Acceptance Filter Mask — Filter mask for the message ID acceptance filter. MIDAFMSK PXR40 Microcontroller Reference Manual, Rev. 1 22-60 Freescale Semiconductor...
Page 645: Receive Fifo Frame Id Rejection Filter Value Register (Rffidrfvr)
Figure 22-64. Receive FIFO Range Filter Configuration Register (RFRFCFR) This register provides access to the four internal frame ID range filter boundary registers of the selected FIFO. For details on frame ID range filter see Section 22.6.9.9, FIFO Filtering. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-61...
Page 646: Receive Fifo Range Filter Control Register (Rfrfctr)
F2EN Range Filter 2 Enable — This control bit is used to enable and disable the frame ID range filter 2. 0 range filter 2 disabled 1 range filter 2 enabled PXR40 Microcontroller Reference Manual, Rev. 1 22-62 Freescale Semiconductor...
Page 647: Last Dynamic Transmit Slot Channel A Register (Ldtxslar)
Number of the last transmission slot in the dynamic segment for channel B. If no frame was transmitted during the dynamic segment on channel B the value of this field is set to 0. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-63...
Page 648: Protocol Configuration Registers
2-bytes max_payload_length_dynamic pPayloadLengthDynMax 2-bytes first_minislot_action_point_offset max(gdActionPointOffset, gdMinislotActionPointOffset) - 1 allow_halt_due_to_clock pAllowHaltDueToClock bool allow_passive_to_active pAllowPassiveToActive cyclepairs PXR40 Microcontroller Reference Manual, Rev. 1 22-64 Freescale Semiconductor...
Page 649 0x7FF number T extern_offset_correction pExternOffsetCorrection T extern_rate_correction pExternRateCorrection See FlexRay Communications System Protocol Specification, Version 2.1 Rev A for detailed protocol parameter definitions Table 22-78. Wakeup Channel Selection wakeup_channel Wakeup Channel PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-65...
Page 650 Reset Figure 22-71. Protocol Configuration Register 3 (PCR3) 22.5.2.67.5 Protocol Configuration Register 4 (PCR4) Base + 0x00A8 Write: POC:config cas_rx_low_max wakeup_symbol_rx_window Reset Figure 22-72. Protocol Configuration Register 4 (PCR4) PXR40 Microcontroller Reference Manual, Rev. 1 22-66 Freescale Semiconductor...
Page 651 Figure 22-76. Protocol Configuration Register 8 (PCR8) 22.5.2.67.10 Protocol Configuration Register 9 (PCR9) Base + 0x00B2 Write: POC:config mini bol_ slot_ offset_correction_out exists dow_ exists Reset Figure 22-77. Protocol Configuration Register 9 (PCR9) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-67...
Page 652 Reset Figure 22-80. Protocol Configuration Register 12 (PCR12) 22.5.2.67.14 Protocol Configuration Register 13 (PCR13) Base + 0x00BA Write: POC:config first_minislot_action_point_offset static_slot_after_action_point Reset Figure 22-81. Protocol Configuration Register 13 (PCR13) PXR40 Microcontroller Reference Manual, Rev. 1 22-68 Freescale Semiconductor...
Page 653 POC:config noise_listen_timeout[15:0] Reset Figure 22-85. Protocol Configuration Register 17 (PCR17) 22.5.2.67.19 Protocol Configuration Register 18 (PCR18) Base + 0x00C4 Write: POC:config wakeup_pattern key_slot_id Reset Figure 22-86. Protocol Configuration Register 18 (PCR18) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-69...
Page 654 POC:config comp_accepted_startup_range_a micro_per_cycle[19:16 Reset Figure 22-90. Protocol Configuration Register 22 (PCR22) 22.5.2.67.24 Protocol Configuration Register 23 (PCR23) Base + 0x00CE Write: POC:config micro_per_cycle[15:0] Reset Figure 22-91. Protocol Configuration Register 23 (PCR23) PXR40 Microcontroller Reference Manual, Rev. 1 22-70 Freescale Semiconductor...
Page 655 Reset Figure 22-95. Protocol Configuration Register 27 (PCR27) 22.5.2.67.29 Protocol Configuration Register 28 (PCR28) Base + 0x00D8 Write: POC:config R dynamic_slot macro_after_offset_correction _idle_phase Reset Figure 22-96. Protocol Configuration Register 28 (PCR28) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-71...
Page 656: Message Buffer Configuration, Control, Status Registers (Mbccsrn)
If the application writes 1 to the EDT bit, no write access to the other register bits is performed. If the application writes 0 to the EDT bit and 1 to the LCKT bit, no write access to the other bits is performed. PXR40 Microcontroller Reference Manual, Rev. 1 22-72 Freescale Semiconductor...
Page 657 0 No such event 1 Slot status field updated or transmit message buffer just enabled PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-73...
Page 658: Message Buffer Cycle Counter Filter Registers (Mbccfrn)
A store first valid frame store first valid frame received on channel A received on channel A no frame transmission no frame transmission no frame stored no frame stored PXR40 Microcontroller Reference Manual, Rev. 1 22-74 Freescale Semiconductor...
Page 659: Message Buffer Frame Id Registers (Mbfidrn)
The application writes the index of the initially associated message buffer header field into this register. The controller updates this register after frame reception or transmission. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-75...
Page 660: Message Buffer Header Field
Frame Header The frame header occupies the first six bytes in the message buffer header field. It contains all FlexRay frame header related information according to the FlexRay Communications System Protocol PXR40 Microcontroller Reference Manual, Rev. 1 22-76 Freescale Semiconductor...
Page 661: Message Buffer Data Field
The individual message buffers are used for all types of frame transmission and for dedicated frame reception based on individual filter settings for each message buffer. The controller supports three types of individual message buffers, which are described in Section 22.6.6, Individual Message Buffer Functional Description. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-77...
Page 662 2 * MBDSR[MBSEG1DS] bytes • the minimum length of the message buffer data field for individual message buffers assigned to the second segment is 2 * MBDSR[MBSEG2DS] bytes. PXR40 Microcontroller Reference Manual, Rev. 1 22-78 Freescale Semiconductor...
Page 663: Receive Shadow Buffers
Figure 22-105. Receive Shadow Buffer Structure 22.6.3.3 Receive FIFO The receive FIFO implements a frame reception system based on the FIFO concept. The controller provides two independent receive FIFOs, one per channel. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-79...
Page 664 FIFO in the flexray memory is determined according to Equation 22-6. SADR_MBHF[n] = (10 * (RFSIR[SIDX] + RFDSR[FIFO_DEPTH])) + SMBA Eqn. 22-6 NOTE All message buffer header fields assigned to a receive FIFO must be a contiguous region. PXR40 Microcontroller Reference Manual, Rev. 1 22-80 Freescale Semiconductor...
Page 665: Message Buffer Configuration And Control Data
The MBSEG2DS and MBSEG1DS fields define the minimum length of the message buffer data field with respect to the message buffer segment. • Message Buffer Segment Size and Utilization Register (MBSSUTR) The LAST_MB_SEG1 and LAST_MB_UTIL fields define the segmentation of the individual PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-81...
Page 666: Individual Message Buffer Control Data
Receive FIFO System Memory Base Address Register (RFSYMBADR) • Receive FIFO Periodic Timer Register (RFPTR) Each FIFO has its own set of configuration data. The configuration data are located in the following registers: PXR40 Microcontroller Reference Manual, Rev. 1 22-82 Freescale Semiconductor...
Page 667: Flexray Memory Layout
The flexray memory starts at a 16 byte boundary The flexray memory contains three areas: the message buffer header area, the message buffer data area, and the sync frame table area. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-83...
Page 668: Flexray Memory Layout (Mcr[Fam] = 1)
• The flexray memory consists of two contiguous regions. • The size of each region is maximum 64 Kbytes. • Each region start at a 16 byte boundary. PXR40 Microcontroller Reference Manual, Rev. 1 22-84 Freescale Semiconductor...
Page 669: Message Buffer Header Area (Mcr[Fam] = 0)
2. The start byte address SADR_MBHF of each message buffer header field for the FIFO must fulfill Equation 22-8. SADR_MBHF = (i * 10) + SYMDARD[SMBA]; (0 <= i < 1024) Eqn. 22-8 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-85...
Page 670: Message Buffer Header Area (Mcr[Fam] = 1)
To ensure data consistency of the physical message buffers, the application must follow the write access scheme that is given in the description of each of the physical message buffer fields. PXR40 Microcontroller Reference Manual, Rev. 1 22-86 Freescale Semiconductor...
Page 671: Message Buffer Header Field Description
Figure 22-110. Frame Header Structure (Transmit Message Buffer) The structure of the frame header in the message buffer header field for transmit message buffers assigned to key slot is given in Figure 22-111. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-87...
Page 672 A syntactically and semantically correct frame is generated with payload_length_static payload words and the payload length field in the transmitted frame header set to payload_length_static. PXR40 Microcontroller Reference Manual, Rev. 1 22-88 Freescale Semiconductor...
Page 673 Frame ID — This field is checked as described in Frame Header Checks. CYCCNT Cycle Count — This field is not used, the value of the transmitted Cycle Count field is taken from the internal communication cycle counter. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-89...
Page 674 Receive FIFO Channel A Message Buffer Figure 22-113 Receive FIFO Channel B Message Buffer Figure 22-114 The meaning of the bits in the slot status structure is explained in Table 22-88. PXR40 Microcontroller Reference Manual, Rev. 1 22-90 Freescale Semiconductor...
Page 675 0 first valid frame received on channel A, or no valid frame received at all 0 first valid frame received on channel B Valid Frame on Channel A — protocol related variable: vSS!ValidFrame channel A vSS!ValidFrame vSS!ValidFrame PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-91...
Page 676 The meaning of the bits in the slot status structure is described in Table 22-88. R VFB Reset – – – – – – – – – – – – – – – – Figure 22-115. Transmit Message Buffer Slot Status Structure (ChAB) PXR40 Microcontroller Reference Manual, Rev. 1 22-92 Freescale Semiconductor...
Page 677 A vRF!Header!SyFIndicator vRF!Header!SyFIndicator Null Frame Indicator Channel A — protocol related variable: vRF!Header!NFIndicator channel A vRF!Header!NFIndicator vRF!Header!NFIndicator Startup Frame Indicator Channel A — protocol related variable: vRF!Header!SuFIndicator channel A vRF!Header!SuFIndicator vRF!Header!SuFIndicator PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-93...
Page 678: Message Buffer Data Field Description
The message buffer data field is located in the flexray memory; thus, the controller has no means to control application write access to the field. To ensure data consistency, the application must follow a write and read access scheme. PXR40 Microcontroller Reference Manual, Rev. 1 22-94 Freescale Semiconductor...
Page 679: Individual Message Buffer Functional Description
Note: The MID and NMV bytes replace the corresponding DATA bytes. 22.6.6 Individual Message Buffer Functional Description The controller provides three basic types of individual message buffers: 1. Single Transmit Message Buffers 2. Double Transmit Message Buffers 3. Receive Message Buffers PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-95...
Page 680: Individual Message Buffer Configuration
Configuration, Control, Status Registers (MBCCSRn) as given in Table 22-94. Table 22-94. Individual Message Buffer Types MBCCSRn[MTD] MBCCSRn[MBT] Individual Message Buffer Description Receive Message Buffer Reserved Single Transmit Message Buffer Double Transmit Message Buffer PXR40 Microcontroller Reference Manual, Rev. 1 22-96 Freescale Semiconductor...
Page 681: Single Transmit Message Buffers
22-119. A description of the regions is given in Table 22-95. If an region is active as indicated in Table 22-96, the access scheme given for that region applies to the message buffer. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-97...
Page 682 The internal status information is not visible to the application. 22.6.6.2.2 Message Buffer States This section describes the transmit message buffer states and provides a state diagram. PXR40 Microcontroller Reference Manual, Rev. 1 22-98 Freescale Semiconductor...
Page 683 Message Transmission - Message buffer data transmit. Payload data from buffer transmitted CCSu – Status Update - Message buffer status update. Update of status flags, the slot status field, and the header index. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-99...
Page 684 In case of a dynamic slot, pLatestTx is not exceeded. status updated Status Updated - Slot Status field and message buffer status flags updated. Interrupt flag set. static slot start Static Slot Start - Start of static slot. PXR40 Microcontroller Reference Manual, Rev. 1 22-100 Freescale Semiconductor...
Page 685 22-97. The state change is indicated through the MBCCSRn[EDS] and MBCCSRn[LCKS] status bits. If the transmit message buffer enters one of the states HDis, HDisLck, HLck, HLckCCSa, HLckCCMa, or HLckCCMa the MBCCSRn[DVAL] flag is negated. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-101...
Page 686 The message buffer data field size, as defined by the related field of the Message Buffer Data Size Register (MBDSR) • The value of the PLDLEN field in the message buffer header field, as described in Section 22.6.5.2.1, Frame Header Description PXR40 Microcontroller Reference Manual, Rev. 1 22-102 Freescale Semiconductor...
Page 687 A transmit message buffer timing and state change diagram for null frame transmission for this case is given in Figure 22-125. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-103...
Page 688 The controller will not clear the MBCCSRn[CMT] flag at the end of transmission and will set the valid flag MBCCSRn[DVAL] to indicate that the message will be transmitted again. PXR40 Microcontroller Reference Manual, Rev. 1 22-104 Freescale Semiconductor...
Page 689: Receive Message Buffers
22-127. A description of the regions is given in Table 22-100. If an region is active as indicated in Table 22-101, the access scheme given for that region applies to the message buffer. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-105...
Page 690 The status bits MBCCSRn[EDS] and MBCCSRn[LCKS] provide the application with the required status information. The internal status information is not visible to the application. PXR40 Microcontroller Reference Manual, Rev. 1 22-106 Freescale Semiconductor...
Page 691 (MBCCSRn). Only one command can be issued with one write access. Each command is executed immediately. If the command is ignored, it must be issued again. Message Buffer Enable and Disable PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-107...
Page 692 For example, if the message buffer is in the buffer subscribed state CCBs and the module triggers the slot start transition SLS at the PXR40 Microcontroller Reference Manual, Rev. 1 22-108 Freescale Semiconductor...
Page 693 PE the message buffer is updated. The message buffer update depends on the slot status bits and the segment the message buffer is assigned to. This is described in Table 22-105. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-109...
Page 694 The amount of message data written into the message buffer data field of the receive shadow buffer is determined by the following two items: 1. the message buffer segment that the message buffer is assigned to, as defined by the Message Buffer Segment Size and Utilization Register (MBSSUTR). PXR40 Microcontroller Reference Manual, Rev. 1 22-110 Freescale Semiconductor...
Page 695: Double Transmit Message Buffer
(MBIDXRn). Instead, the index of the message buffer header field must be fetched from the Message Buffer Index Registers (MBIDXRn). 22.6.6.4 Double Transmit Message Buffer The section provides a detailed description of the functionality of the double transmit message buffers. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-111...
Page 696 22-131. The given regions represent fields that can be accessed from both the application and the controller and, thus, require access restrictions. A description of the regions is given in Table 22-106. PXR40 Microcontroller Reference Manual, Rev. 1 22-112 Freescale Semiconductor...
Page 697 The states for the commit side of a double transmit message buffer are given in Figure 22-132. A description of the states is given in Table 22-108. The states for the transmit side of a PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-113...
Page 698 Disabled and Locked - Message Buffer under configuration. Commit Side can not be used for internal message transfer. HLck Locked - Applications access to data, control, and status. Commit Side can not be used for internal message transfer. PXR40 Microcontroller Reference Manual, Rev. 1 22-114 Freescale Semiconductor...
Page 699 – Message Available and Internal Message Transfer - Message buffer is assigned to next slot and cycle counter filter matches and Message Buffer Data transferred from commit side to transmit side. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-115...
Page 700 MBCCSR(2n+1)[EDS] = 0 Application triggers message buffer enable. MBCCSR(2n+1)[EDT]:=1 MBCCSR(2n+1)[EDS] = 1 Application triggers message buffer disable. MBCCSR(2n)[LCKS] = 0 Application triggers message buffer lock. MBCCSR(2n)[LCKT]:=1 MBCCSR(2n)[LCKS] = 1 Application triggers message buffer unlock. PXR40 Microcontroller Reference Manual, Rev. 1 22-116 Freescale Semiconductor...
Page 701 Idle MA > SA Message Available > Slot Assigned CCMa TX > STS Transmission Slot Start > Static Slot Start TX > DSS Transmission Slot Start > Dynamic Slot Start PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-117...
Page 702 3. the transmit side is in one of the states Idle, CCSa, or CCMa 4. the transmit side contains either no valid message data, i.e. MBCCSR(2n+1)[CMT] = 0 or the message data were transmitted at least once, i.e. MBCCSR(2n+1)[DVAL] = 1 PXR40 Microcontroller Reference Manual, Rev. 1 22-118 Freescale Semiconductor...
Page 703 HLck Idle Idle HLck internal message transfer overwrites non-transmitted message CCITx CCITx Idle Idle Idle search[s+1] slot s slot s+1 slot s+2 Figure 22-135. Internal Message Transfer in Immediate Commit Mode PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-119...
Page 704: Individual Message Buffer Search
22-112. For the dynamic segment only those message buffers are considered, that match the condition of at least one row of Table 22-113. These message buffers are called matching message buffers. PXR40 Microcontroller Reference Manual, Rev. 1 22-120 Freescale Semiconductor...
Page 705: Message Buffer Cycle Counter Filtering
PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-121...
Page 706: Message Buffer Channel Assignment Consistency
POC:config state. This is referred to as individual message buffer reconfiguration. The configuration bits and fields that can be changed are given in the section on Specific Configuration Data. PXR40 Microcontroller Reference Manual, Rev. 1 22-122 Freescale Semiconductor...
Page 707: Reconfiguration Schemes
RX single TX double TX (commit side) double TX (transmit side) Figure 22-137. Message Buffer Reconfiguration Scheme 22.6.9 Receive FIFOs This section provides the functional description of the two receive FIFOs. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-123...
Page 708: Overview
Configure the Receive FIFO Depth and Size Register (RFDSR) with FIFO entry size • Configure the Receive FIFO Depth and Size Register (RFDSR) with FIFO depth • Configure the FIFO Filters PXR40 Microcontroller Reference Manual, Rev. 1 22-124 Freescale Semiconductor...
Page 709: Fifo Periodic Timer
The FIFOA (FIFOB) contains valid messages if the FIFO fill level FLA (FLB) is greater than 0. The Receive FIFO A Read Index Register (RFARIR) (Receive FIFO B Read Index Register (RFBRIR)) pointing to a message buffer with valid content and the oldest frames stored in the FIFO. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-125...
Page 710: Fifo Update
The FIFO will not receive invalid or null-frames. For each FIFO filter, the pass criteria is specified in the related section given below. Only frames that have passed all filters will be appended to the FIFO. The FIFO filter path is depicted in Figure 22-138. PXR40 Microcontroller Reference Manual, Rev. 1 22-126 Freescale Semiconductor...
Page 711 Dynamic Segment Message ID (vRF!Header!PPIndicator=1) Message ID Else Acceptance Filter Passed FIFO full Append to FIFO ( Set FIFO Overflow Interrupt Flag Ignore frame Figure 22-138. Received Frame FIFO Filter Path PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-127...
Page 712 Receive FIFO Range Filter Control Register (RFRFCTR). The RX FIFO Frame ID range filters apply to all received valid frames. A received frame with the frame ID FID passes the RX FIFO Frame ID Range PXR40 Microcontroller Reference Manual, Rev. 1 22-128 Freescale Semiconductor...
Page 713: Channel Device Modes
FlexRay port consisting of FR_A_RX, FR_A_TX, and FR_A_TX_EN is connected to the physical bus channel A and the FlexRay port consisting of FR_B_RX, FR_B_TX, and FR_B_TX_EN is connected to the physical bus channel B. The dual channel system is shown in Figure 22-139. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-129...
Page 714: Single Channel Device Mode
Port A is connected to a FlexRay Channel B. The two FlexRay channels differ only in the initial value for the frame CRC cCrcInit. For a single channel device, the application can access and configure only the registers related to internal channel A. PXR40 Microcontroller Reference Manual, Rev. 1 22-130 Freescale Semiconductor...
Page 715: External Clock Synchronization
EOC_AP and ERC_AP fields in the Protocol Operation Control Register (POCR). The PE applies the external correction values in the next even-odd cycle pair as shown in Figure 22-142 Figure 22-143. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-131...
Page 716: Sync Frame Id And Sync Frame Deviation Tables
NOTE Only synchronization frames that have passed the synchronization frame filters are considered for clock synchronization and appear in the sync frame tables. PXR40 Microcontroller Reference Manual, Rev. 1 22-132 Freescale Semiconductor...
Page 717: Sync Frame Id Table Content
The application must provide the appropriate amount of flexray memory for the tables. The memory layout of the tables is given in Figure 22-144. Each table occupies 120 16-bit entries. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-133...
Page 718: Sync Frame Id And Sync Frame Deviation Table Generation
The number of available table entries per channel is provided in the SFCNTR.SFEVA and SFCNTR.SFEVB fields. The application can now start to read the sync table data from the locations given Figure 22-144. PXR40 Microcontroller Reference Manual, Rev. 1 22-134 Freescale Semiconductor...
Page 719: Sync Frame Table Access
MTE control bit during the static segment of the preceding communication cycle. The MTS is transmitted over channel A in the communication cycle with number CYCCNT, if Equation 22-20, Equation 22-21, and Equation 22-21 are fulfilled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-135...
Page 720: Key Slot Transmission
22.6.15 Sync Frame Filtering Each received synchronization frame must pass the Sync Frame Acceptance Filter and the Sync Frame Rejection Filter before it is considered for clock synchronization. If the synchronization frame filtering is PXR40 Microcontroller Reference Manual, Rev. 1 22-136 Freescale Semiconductor...
Page 721: Sync Frame Acceptance Filtering
To read out the current settings for a strobe signal with number N, the application must execute the following sequence. 1. Write to STBSCR with WMD = 1 and SEL = N. (updates SEL field only) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-137...
Page 722: Strobe Signal Timing
If the protocol is not in one of these modes, the timers are stopped. The application must restart the timers when the protocol has reached the POC:normal active POC:normal passive state. PXR40 Microcontroller Reference Manual, Rev. 1 22-138 Freescale Semiconductor...
Page 723: Absolute Timer T1
0. At the macrotick start event, the value of MT[31:0] is checked and then decremented. Thus, if the timer is started with MT[31:0] == 0, it expires at the next macrotick start. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-139...
Page 724: Slot Status Monitoring
Figure 22-148. Slot Status Vector Update NOTE The slot status for the NIT of cycle n is provided after the start of cycle n+1. PXR40 Microcontroller Reference Manual, Rev. 1 22-140 Freescale Semiconductor...
Page 725: Channel Status Error Counter Registers
NIT are taken into account. The counters wrap round after they have reached the maximum value. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-141...
Page 726: Protocol Status Registers
The increment condition for each slot status counter consists of two parts, the frame related condition part and the slot related condition part. The internal slot status counter SSCRn_INT is incremented if at least one of the conditions is fulfilled: 1. frame related condition: PXR40 Microcontroller Reference Manual, Rev. 1 22-142 Freescale Semiconductor...
Page 727: Message Buffer Slot Status Field
The behavior of the controller after the occurrence of a system bus failure is defined by the SBFF bit in Module Configuration Register (MCR). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-143...
Page 728: System Bus Illegal Address Access
Each individual message buffer provides an interrupt flag MBCCSn[MBIF] and an interrupt enable bit MBCCSn[MBIE]. The controller sets the interrupt flag when the slot status of the message buffer was updated. If the interrupt enable bit is asserted, an interrupt request is generated. PXR40 Microcontroller Reference Manual, Rev. 1 22-144 Freescale Semiconductor...
Page 729: Combined Interrupt Sources
22.6.20.2.3 Protocol Interrupt The combined protocol interrupt request PRTIRQ is generated when at least one of the individual protocol interrupt sources generates an interrupt request and the interrupt enable bit GIFER.PRIE is set. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-145...
Page 730 22.6.20.2.5 Module Interrupt The combined module interrupt request MIRQ is generated if at least one of the combined interrupt sources generates an interrupt request and the interrupt enable bit GIFER.MIE is set. PXR40 Microcontroller Reference Manual, Rev. 1 22-146 Freescale Semiconductor...
Page 731 GIFER[TBIE] Transmit GIFER[CHIF] CHIIRQ GIFER[PRIF] PRTIRQ & GIFER[PRIE] GIFER[FAFAIF] FAFAIRQ & GIFER[FAFAIE] GIFER[FAFBIF] FAFBIRQ & GIFER[FAFBIE] GIFER[WUPIF] WUPIRQ & GIFER[WUPIE] GIFER[MIF] MIRQ & GIFER[MIE] Figure 22-150. Scheme of cascaded interrupt request PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-147...
Page 732: Lower Bit Rate Support
The application configures the FlexRay channel bit rate by setting the BITRATE field in the Module Configuration Register (MCR). The protocol values are set internally. The available bit rates, the related BITRATE field configuration settings and related protocol parameter values are shown in Table 22-117. PXR40 Microcontroller Reference Manual, Rev. 1 22-148 Freescale Semiconductor...
Page 733: Application Information
1 to the module enable bit MEN in the Module Configuration Register (MCR) The controller now enters the Normal Mode. The application can commence with the protocol initialization described in Section 22.7.1.2, Protocol Initialization. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-149...
Page 734: Protocol Initialization
This section describes the relationship between the number of message buffers that can be utilized and the required minimum CHI clock frequency. Additional constraints for the minimum CHI clock frequency are given in Section 22.3, Controller Host Interface Clocking. PXR40 Microcontroller Reference Manual, Rev. 1 22-150 Freescale Semiconductor...
Page 735: Protocol Control Command Execution
The PE maintains a protocol command vector. For each command that was accepted by the PE, the PE sets the corresponding command bit in the protocol command vector. If a command is issued while the corresponding command bit is set, the command is not queued and is lost. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-151...
Page 736: Message Buffer Search On Simple Message Buffer Configuration
S. The simple configuration used in this section utilizes two message buffers, one single buffered transmit message buffer and one receive message buffer. The transmit message buffer has the message buffer number t and has following configuration PXR40 Microcontroller Reference Manual, Rev. 1 22-152 Freescale Semiconductor...
Page 737 Furthermore the assumption is that both message buffers are enabled (MBCCSRt[EDS] = 1 and MBCCSRr[EDS] = 1) NOTE The cycle set {4n+2} = {2,6,10,...} is assigned to the receive buffer only. The cycle set {4n} = {0,4,8,12,...} is assigned to both buffers. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-153...
Page 738: Behavior In Static Segment
If transmit data are available, i.e. the transmit buffer is committed MBCCSRt[CMT]=1 and not locked MBCCSRt[LCKS]=0, a) for the cycles in the set {4n}, which is assigned to both buffers, the transmit buffer will be found and the node transmits data. PXR40 Microcontroller Reference Manual, Rev. 1 22-154 Freescale Semiconductor...
Page 739 {4n+2}, which is assigned to the receive buffer only, the receive buffer will be found and the node can receive data. The receive and transmit cycles are shown in Figure 22-153 Figure 22-154. Transmit Data Not Available PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 22-155...
Page 740 FlexRay Communication Controller (FLEXRAY) PXR40 Microcontroller Reference Manual, Rev. 1 22-156 Freescale Semiconductor...
Page 741: Introduction
The PXR40 has one eMIOS200 module that implements 24-bitcounters. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-1...
Page 742: Block Diagram
• • • Channel[8] EMIOS[8] Channel[7] EMIOS[7] Counter • • Buses • • • • (Time Output Disable Bases) Channel[0] Control Bus EMIOS[0] eMIOS Channel Flags Figure 23-1. eMIOS200 Block Diagram PXR40 Microcontroller Reference Manual, Rev. 1 23-2 Freescale Semiconductor...
Page 743: Features
IP interface. 23.1.4 eMIOS200 Channel Configurations Table 23-1 lists the eMIOS modes supported on the unified channels for this device. All included modes are on all channels. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-3...
Page 744 23.4.1.1.14/23-43 Center-Aligned Output PWM with Dead Time OPWMC 23.4.1.1.15/23-48 Center-Aligned Output PWM Buffered with Dead Time OPWMCB 23.4.1.1.16/23-51 Output Pulse Width Modulation OPWM 23.4.1.1.18/23-58 Output Pulse Width Modulation Buffered OPWMB 23.4.1.1.18/23-58 PXR40 Microcontroller Reference Manual, Rev. 1 23-4 Freescale Semiconductor...
Page 745: External Signal Description
Each output pin may be disabled by the assertion of a selected eMIOS channel FLAG bit from the EMIOS_GFR register described in 23.3.2.2/23-9. The choice of FLAG is defined by the ODIS and ODISSL bit fields of the EMIOS_CCR[n] described in section 23.3.2.7/23-12 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-5...
Page 746: Memory Map And Register Description
EMIOS_CCR[1]—Control Register 0x0000_0000 23.3.2.7/23-12 0x0050 EMIOS_CSR[1]—Status Register 0x0000_0000 23.3.2.8/23-18 0x0054 EMIOS_ALTA[1] —Alternate A Register 0x0000_0000 23.3.2.9/23-19 0x0058–0x005F Reserved Unified Channel 2 Registers 0x0060 EMIOS_CADR[2]—A Register 0x0000_0000 23.3.2.4/23-10 0x0064 EMIOS_CBDR[2]—B Register 0x0000_0000 23.3.2.5/23-11 PXR40 Microcontroller Reference Manual, Rev. 1 23-6 Freescale Semiconductor...
Page 747 Unified Channel 12 0x01A0 Unified Channel 28 0x03A0 Unified Channel 13 0x01C0 Unified Channel 29 0x03C0 Unified Channel 14 0x01E0 Unified Channel 30 0x03E0 Unified Channel 15 0x0200 Unified Channel 31 0x0400 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-7...
Page 748: Register Descriptions
If ETB is set to select STAC as the counter bus[A] source, the GTBE must be set to enable the STAC to counter bus[A]. See the STAC bus configuration register (ETPU_REDCR) section of the eTPU chapter for more information about the STAC. PXR40 Microcontroller Reference Manual, Rev. 1 23-8 Freescale Semiconductor...
Page 749: Emios200 Global Flag Register (Emios_Gfr)
0000_0011 1111_1110 1111_1111 24–31 Reserved 23.3.2.2 eMIOS200 Global Flag Register (EMIOS_GFR) Offset: EMIOS_BASE + 0x0004 Access: User read-only R F31 Reset R F15 Reset Figure 23-3. eMIOS200 Global Flag Register (EMIOS_GFR) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-9...
Page 750: Emios200 Output Update Disable Register (Emios_Oudr)
EMIOS_CADR[n]. A1 and A2 are cleared by reset. Table 23-7 summarizes the EMIOS_CADR[n] writing and reading accesses for all operation modes. For more information see Section 23.4.1.1, Unified Channel Modes of Operation. PXR40 Microcontroller Reference Manual, Rev. 1 23-10 Freescale Semiconductor...
Page 751: Emios200 B Register (Emios_Cbdr[N])
— — — — — — DAOC — — — — — — QDEC — — WPTA — — — OPWFM — — OPWMC — — OPWM — — — — PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-11...
Page 752: Emios200 Counter Register (Emios_Ccntr[N])
23.3.2.7 eMIOS200 Control Register (EMIOS_CCR[n]) Offset: UC[n] base address + 0x000C Access: User read/write FREN ODIS ODISSL UCPRE PREN Reset FORC FORC MODE Reset Figure 23-8. eMIOS200 Control Register (EMIOS_CCR[n]) PXR40 Microcontroller Reference Manual, Rev. 1 23-12 Freescale Semiconductor...
Page 753 Direct Memory Access Bit. The DMA bit selects whether the FLAG generation is used as an interrupt or as a DMA request. 0 FLAG/overrun assigned to interrupt request. 1 FLAG/overrun assigned to DMA request. Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-13...
Page 754 B, otherwise it has no effect. 0 Has no effect. 1 Force a match at comparator B. For input modes, the FORCMB bit is not used and writing to it has no effect. Reserved PXR40 Microcontroller Reference Manual, Rev. 1 23-14 Freescale Semiconductor...
Page 755 For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match. 0 The EDPOL value is transferred to the output flip-flop. 1 The output flip-flop is toggled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-15...
Page 756 Double Action Output compare (with FLAG set on both match) 000_1000 Pulse/Edge Accumulation (continuous) 000_1001 Pulse/Edge Accumulation (single-shot) 000_1010 Pulse/Edge Counting (continuous) 000_1011 Pulse/Edge Counting (single-shot) 000_1100 QDEC Quadrature Decode (for count & direction encoders type) PXR40 Microcontroller Reference Manual, Rev. 1 23-16 Freescale Semiconductor...
Page 757 Modulus Counter Buffered (Up counter with clear on match start, internal clock) 101_0001 Modulus Counter Buffered (Up counter with clear on match start, external clock) 101_0010 – 101_0011 Reserved 101_0100 Modulus Counter Buffered (Up/Down counter with flag on A match, internal clock) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-17...
Page 758: Emios200 Status Register (Emios_Csr[N])
110_0011 – 111_1111 Reserved 23.3.2.8 eMIOS200 Status Register (EMIOS_CSR[n]) Offset: UC[n] base address + 0x0010 Access: User read/write Reset R OVFL UCIN UCOUT FLAG Reset Figure 23-9. eMIOS200 Status Register (EMIOS_CSR[n]) PXR40 Microcontroller Reference Manual, Rev. 1 23-18 Freescale Semiconductor...
Page 759: Emios200 Alternate A Register (Emios_Alta[N])
The EMIOS_ALTA[n] register provides an alternate read-only address to access A2 channel registers in GPIO, PEC, WPTA, and OPWMT modes. If the EMIOS_CADR[n] register is used with EMIOS_ALTA[n], both A1 and A2 registers can be accessed in these modes. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-19...
Page 760: Functional Description
Programmable input edge detector, which detects the rising, falling or either edges • An output flip-flop, which holds the logic level to be applied to the output pin • eMIOS200 status and control register PXR40 Microcontroller Reference Manual, Rev. 1 23-20 Freescale Semiconductor...
Page 761 Control Signals ips_byte[23:16] ips_byte[31:24] channel_datapath ips_rwb uc_cnt_rd_data[n] ips_addr[29:27] Comparator A Counter Bus Comparator B emios_counter_bus[0] emios_counter_bus[1] uc_cnt_rd_data[n] Figure 23-11. Unified Channel Block Diagram Figure 23-12 shows the unified channel control block diagram. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-21...
Page 762: Unified Channel Modes Of Operation
(EMIOS_CCNTR[n] register) is cleared and disabled. All control bits remain accessible. In order to prepare the unified channel for a new operation mode, writing to registers EMIOS_CADR[n] or EMIOS_CBDR[n] stores the same value in registers A1/A2 or B1/B2, respectively. PXR40 Microcontroller Reference Manual, Rev. 1 23-22 Freescale Semiconductor...
Page 763 0x001250 0x001525 0x0016A0 Counter Bus FLAG Pin/Register A2 (Captured) Value 0xxxxxxx 0x001000 0x001250 0x0016A0 Notes: 1. After input filter 2. EMIOS_CADR[n]  A2 Figure 23-13. SAIC with Rising Edge Triggering Example PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-23...
Page 764 (see Figure 23-17). NOTE In SAOC mode, the internal channel counter is free-running, and starts counting as soon as the SAOC mode is entered. PXR40 Microcontroller Reference Manual, Rev. 1 23-24 Freescale Semiconductor...
Page 765 0x000001 0x000002 0x000000 0x000001 0x000002 System Clock A1 Match FLAG Set Event FLAG Pin/Register FLAG Clear A2 Value 0x000001 Note: 1. EMIOS_CADR[n]  A2 Figure 23-17. SAOC Example with Flag Behavior PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-25...
Page 766 B1 register is loaded with the A1 register content. This guarantees that the data in register B1 always has the coherent data related to the last EMIOS_CADR[n] read. The B1 register updates remain PXR40 Microcontroller Reference Manual, Rev. 1 23-26 Freescale Semiconductor...
Page 767 To allow coherent data, reading EMIOS_CADR[n] forces A1 content be transferred to B1 register and disables transfers between B2 and B1. These transfers are disabled until the next read of the PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-27...
Page 768 0x001250 0xxxxxxx 0x001000 0x001000 0x001250 B1 Value Notes: 1. After input filter 2. EMIOS_CADR[n] = A2 3. EMIOS_CBDR[n] = B1 Figure 23-21. A1 and B1 Updates at EMIOS_CADR[n] and EMIOS_CBDR[n] Reads PXR40 Microcontroller Reference Manual, Rev. 1 23-28 Freescale Semiconductor...
Page 769 Figure 23-22 Figure 23-23 show how the unified channel can be used to generate a single output pulse with FLAG bit being set on the second match or on both matches, respectively. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-29...
Page 770 1. EMIOS_CADR[n] = A1 2. EMIOS_CBDR[n] = B1 A2 = A1 according to OU[n] bit B2 = B1 according to OU[n] bit Figure 23-23. DAOC with FLAG Set on Both Matches PXR40 Microcontroller Reference Manual, Rev. 1 23-30 Freescale Semiconductor...
Page 771 EMIOS_CADR[n] and EMIOS_CBDR[n] reads will not return coherent data until a new bus capture is triggered to registers A2 and B2. This capture event is indicated by the channel FLAG being asserted. If enabled, the FLAG also generates an interrupt. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-31...
Page 772 1. Cleared on the first input event after writing to register A1 2. After input filter 3. EMIOS_CADR[n] = A1 (when writing) 4. EMIOS_CADR[n] = A2 (when reading) 5. EMIOS_CBDR[n] = B1 Figure 23-25. PEA Continuous Mode Example PXR40 Microcontroller Reference Manual, Rev. 1 23-32 Freescale Semiconductor...
Page 773 The EMIOS_CCNTR content is also transferred to register A2 when a match in the B comparator occurs. Figure 23-27 Figure 23-28 show how the unified channel can be used for continuous or single-shot pulse/edge counting mode. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-33...
Page 774 0x000090 B1 Value 0x000303 0x000303 0x000303 A2 Value   EMIOS_CCNTR[n] EMIOS_CCNTR[n] Notes: 1. EMIOS_CADR[n] = A1 2. EMIOS_CBDR[n] = B1 3. EMIOS_ALTA[n] = A2 Figure 23-28. PEC Single-Shot Mode Example PXR40 Microcontroller Reference Manual, Rev. 1 23-34 Freescale Semiconductor...
Page 775 –1 –1 –1 –1 A1 Write A1 Match EMIOS_CCNTR[n] A1 Match (Value 1) Value 1 0x000000 Time FLAG Pin/Register Note: EMIOS_CADR[n]  A1 Figure 23-29. QDEC Mode Example with Count & Direction Encoder PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-35...
Page 776 B matches, it always contains stable and up-to-date data. In this mode, this register is accessible through the alternate register address EMIOS_ALTA[n]. Figure 23-31 shows how the unified channel can be used to accumulate high time. PXR40 Microcontroller Reference Manual, Rev. 1 23-36 Freescale Semiconductor...
Page 777 At the next prescaler tick after the match, the internal counter remains at 0 and only resumes counting on the following tick. See Figure 23-61 Figure 23-64. • Internal counter clearing on match end (MODE = 001_001b) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-37...
Page 778 0x000200 0x000000 Time FLAG pin/register 0x000200 A1 value 0xxxxxxx 0x000303 0x000303 0x000200 0x000303 Notes: 1. EMIOS_CADR[n] = A1 A2 = A1 according to OU[n] bit Figure 23-32. MC Up Mode Example PXR40 Microcontroller Reference Manual, Rev. 1 23-38 Freescale Semiconductor...
Page 779 A1 values. Register A1 is loaded with the value in A2 at the cycle boundary. Any value written to the A2 register within cycle (n) is updated to A1 at the next cycle PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-39...
Page 780 Figure 23-35. MCB Up/Down Mode Figure 23-36 shows the A1 register update process in up counter mode. The A1 load signal is generated at the last system clock period of a counter cycle. PXR40 Microcontroller Reference Manual, Rev. 1 23-40 Freescale Semiconductor...
Page 781 0x000005 0x000001 Time Selected Counter = 2 A1 Load Signal 0x000006 0x000005 0x000006 A2 Value A1 Value 0x000006 0x000005 0x000006 Figure 23-37. MCB Mode A1 Register Update in Up/Down Counter Mode PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-41...
Page 782 Writing 0x0 to A1 and B1 produces a duty cycle of 0%. Figure 23-38 shows the unified channel running in OPWFM mode with immediate register update and Figure 23-39 shows the unified channel running in OPWFM mode with next period update. PXR40 Microcontroller Reference Manual, Rev. 1 23-42 Freescale Semiconductor...
Page 783 B1 register indicates the frequency. Both A1 and B1 registers are double-buffered to allow smooth signal generation when changing the registers values on the fly. This mode supports 0% and 100% duty cycles. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-43...
Page 784 A1 Match A1 Match Negative Edge Detection B1 Match B1 Match Negative Edge Detection B1 Match Negative Edge Detection Output Pin Figure 23-40. OPWFMB A1 and B1 Match to Output Register Delay PXR40 Microcontroller Reference Manual, Rev. 1 23-44 Freescale Semiconductor...
Page 785 MODE[5] is set. Because the B1 FLAG occurs at the cycle boundary, this flag can be used to indicate that A2 or B2 data written on cycle (n) were loaded to A1 or B1, respectively, thus generating matches in PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-45...
Page 786 EDPOL should be set to 0. Note that both the channel and global prescalers are set to 0x00_0000 (each divide ratio is one), meaning that the channel internal counter transitions at every system clock cycle. PXR40 Microcontroller Reference Manual, Rev. 1 23-46 Freescale Semiconductor...
Page 787 A1 match, thus the output flip-flop is set to the complement of EDPOL bit. This cycle corresponds to a 100% duty cycle signal. The same output signal can be generated for any A1 value greater or equal to B1. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-47...
Page 788 In the next match between register A1 and the selected time base, the output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously. PXR40 Microcontroller Reference Manual, Rev. 1 23-48 Freescale Semiconductor...
Page 789 If A1 and B1 are set to 0x00_0000, a 0% duty cycle waveform is produced. Figure 23-45 Figure 23-46 show the unified channel running in OPWMC with leading and trailing dead time, respectively. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-49...
Page 790 Notes: 1. EMIOS_CADR[n] = A1 2. EMIOS_CBDR[n] = B1 A2 = A1 according to OU[n] bit B2 = B1 according to OU[n] bit Figure 23-46. OPWMC with Trailing Dead Time Insertion PXR40 Microcontroller Reference Manual, Rev. 1 23-50 Freescale Semiconductor...
Page 791 A1 and B1 registers, which occurs when the selected counter bus transitions from 0x00_0002 to 0x00_0001. This event defines the cycle boundary. Values written to A2 or PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-51...
Page 792 PWM signal. Both A1 and B1 register values are changing within the same cycle, which allows to vary at the same time the duty cycle and dead time values. PXR40 Microcontroller Reference Manual, Rev. 1 23-52 Freescale Semiconductor...
Page 793 B1 matches are enabled. When the match between register B1 and the selected time base occurs, the output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-53...
Page 794 EDPOL bit value. NOTE The FORCMA bit set does not set the internal time-base to 0x00_0001 as a regular A1 match. PXR40 Microcontroller Reference Manual, Rev. 1 23-54 Freescale Semiconductor...
Page 795 + 1, which is actually considered to belong to cycle n + 2 and therefore does not cause the output flip-flip to transition. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-55...
Page 796 B, the output flip-flop is set to the complement of the EDPOL bit. FLAG can be generated at match B, when MODE[5] is cleared, or in both matches, when MODE[5] is set. PXR40 Microcontroller Reference Manual, Rev. 1 23-56 Freescale Semiconductor...
Page 797 0xxxxxxx 0x001000 Notes: 1. EMIOS_CADR[n] = A1 2. EMIOS_CBDR[n] = B2 A2 = A1 according to OU[n] bit B2 = B1 according to OU[n] bit Figure 23-51. OPWM with Immediate Update PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-57...
Page 798 A1 = 0 match from cycle(n) has precedence over B1 match from cycle(n – 1) • A1 matches are masked out if they occur after B1 match within the same cycle PXR40 Microcontroller Reference Manual, Rev. 1 23-58 Freescale Semiconductor...
Page 799 B1 = 0x00_0008 negative edge signal. In this case A1 match has precedence over B1 match, causing the output pin to remain at EDPOL bit value, thus generating a 0% duty cycle signal. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-59...
Page 800 A1 or B1 match. The output disable does not modify the flag bit behavior. There is a delay of one system clock between the assertion of the output disable signal and the transition of the output pin to EDPOL. PXR40 Microcontroller Reference Manual, Rev. 1 23-60 Freescale Semiconductor...
Page 801 EDPOL bit at B1 match. If B1 is set to 0x00_0009, for instance, B1 match does not occur, thus a 0% duty cycle signal is generated. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-61...
Page 802: Input Programmable Filter (Ipf)
Counting is enabled by setting the UCPREN bit in the EMIOS_CCR[n]. The counter can be stopped at any time by clearing this bit, thereby stopping the internal counter in the unified channel. PXR40 Microcontroller Reference Manual, Rev. 1 23-62 Freescale Semiconductor...
Page 803: Effect Of Freeze On The Unified Channel
STAC client. There are restrictions on engine export/import targets: one engine cannot export from or import to itself, nor can it import time base and/or angle count if in angle mode. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-63...
Page 804 2. The SRV bits capture TS[01] Figure 23-60. Timing Diagram for the STAC Bus and STAC Client Submodule Output Every time the selected time slot changes, the STAC client submodule output is updated. PXR40 Microcontroller Reference Manual, Rev. 1 23-64 Freescale Semiconductor...
Page 805: Effect Of Freeze On The Stac Client Submodule
The eMIOS200 can generate one interrupt per channel. An interrupt request is generated according to the configuration of the channel and input events or matches. See Chapter 10, Interrupts and Interrupt Controller (INTC), for details on the eMIOS200 interrupt vectors. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-65...
Page 806: Initialization/Application Information
MC mode with internal clock source. In these cases, the counter will skip the next prescaled clock edge and continue incremented on subsequent edges, as shown in Figure 23-62. NOTE MCB, OPWFMB, and OPWMB modes have a different behavior. PXR40 Microcontroller Reference Manual, Rev. 1 23-66 Freescale Semiconductor...
Page 807 When a match occurs, the first clock cycle is used to clear the internal counter, and only after a second edge of prescaled clock the counter will start counting. Figure 23-62. Time Base Period when Running with a Prescaler Ratio Greater Than 1 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-67...
Page 808 FLAG Clear Note: The match occurs only when the input event/prescaler clock enable is active. Then, the internal counter is immediately cleared. Figure 23-65. Time Base Generation with Clear on Match End PXR40 Microcontroller Reference Manual, Rev. 1 23-68 Freescale Semiconductor...
Page 809: Coherent Accesses
Reading the EMIOS_CADR[n] register again in the same period of the last read of EMIOS_CBDR[n] register may lead to incoherent results. This occurs if the last read of EMIOS_CBDR[n] register occurred after a disabled B2 to B1 transfer. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 23-69...
Page 810 Enhanced Modular Input/Output Subsystem (eMIOS200) PXR40 Microcontroller Reference Manual, Rev. 1 23-70 Freescale Semiconductor...
Page 811: Introduction
Message Buffers (MB) and another one for storing Rx Individual Mask Registers. Support for 64 Message Buffers is provided. The functions of the sub-modules are described in subsequent sections. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-1...
Page 812: Overview
A flexible number of Message Buffers (16, 32 or 64) is also supported. The Message Buffers are stored in an embedded RAM dedicated to the FlexCAN module. Please refer to the Device User Guide for the actual number of Message Buffer configured in the MCU PXR40 Microcontroller Reference Manual, Rev. 1 24-2 Freescale Semiconductor...
Page 813: Flexcan Module Features
Global network time, synchronized by a specific message • Maskable interrupts • Independent of the transmission medium (an external transceiver is assumed) • Short latency time due to an arbitration scheme for high-priority messages PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-3...
Page 814: Modes Of Operation
CPU that the clocks can be shut down globally. Exit from this mode happens when the Stop Mode request is removed. PXR40 Microcontroller Reference Manual, Rev. 1 24-4 Freescale Semiconductor...
Page 815: External Signal Description
The FLEXCAN_x_IFLAG2 and FLEXCAN_x_IMASK2 registers are considered reserved space when FlexCAN is configured with 16 or 32 MBs. The Rx Global Mask (FLEXCAN_x_RXGMASK), Rx Buffer 14 Mask (FLEXCAN_x_RX14MASK) and the Rx Buffer 15 Mask (FLEXCAN_x_RX15MASK) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-5...
Page 816 When it is configured with 32 MBs, the memory sizes are 544 and 128 bytes, so the address ranges 0x0280–0x047F and 0x0900–0x097F are considered reserved space. Furthermore, if the MBFEN bit in FLEXCAN_x_MCR is negated, then the whole Rx Individual Mask Registers address range (0x0880–0x097F) is considered reserved space. PXR40 Microcontroller Reference Manual, Rev. 1 24-6 Freescale Semiconductor...
Page 817 — — 0x0280–0x047F Base + Reserved 0x0480-087F Base + RXIMR0-RXIMR15—Rx Individual 24.3.4.13/32 0x0880-0x08BF Mask Registers Base + RXIMR16-RXIMR31—Rx 24.3.4.13/32 0x08C0-0x08FF Individual Mask Registers Base + RXIMR32-RXIMR63—Rx 24.3.4.13/32 0x0900-0x097F Individual Mask Registers PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-7...
Page 818: Message Buffer Structure
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 = Unimplemented or Reserved Figure 24-2. Message Buffer Structure PXR40 Microcontroller Reference Manual, Rev. 1 24-8 Freescale Semiconductor...
Page 819 Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from the CAN bus. For Tx frames, the CPU prepares the data field to be transmitted within the frame. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-9...
Page 820 This code is only valid when AEN bit in FLEXCAN_x_MCR is asserted. MB does not participate in the arbitration process. 1100 1000 Transmit data frame unconditionally once. After transmission, the MB automatically returns to the INACTIVE state. PXR40 Microcontroller Reference Manual, Rev. 1 24-10 Freescale Semiconductor...
Page 821 MBM as a result of match to a remote request frame. The data frame will be transmitted unconditionally once and then the code will automatically return to ‘1010’. The CPU can also write this code with the same effect. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-11...
Page 822: Rx Fifo Structure
ID Table 2 0xEC ID Table 3 0xF0 ID Table 4 0xF4 ID Table 5 0xF8 ID Table 6 0xFC ID Table 7 = Unimplemented or Reserved Figure 24-3. Rx FIFO Structure PXR40 Microcontroller Reference Manual, Rev. 1 24-12 Freescale Semiconductor...
Page 823 Specifies an ID to be used as acceptance criteria for the FIFO. In both standard and extended frame formats, all 8 RXIDC_2 bits of the field are compared to the 8 most significant bits of the received ID. RXIDC_3 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-13...
Page 824: Register Descriptions
(0x80-0xFF) is used by the FIFO engine. See Section 24.3.3, Rx FIFO Structure Section 24.4.7, Rx FIFO, for more information. 0 FIFO not enabled 1 FIFO enabled PXR40 Microcontroller Reference Manual, Rev. 1 24-14 Freescale Semiconductor...
Page 825 See Section 24.4.9.1, Freeze Mode, for more information. 0 FlexCAN not in Freeze Mode, prescaler running 1 FlexCAN in Freeze Mode, prescaler stopped PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-15...
Page 826 Upon reset this bit is negated, allowing legacy software to work without modification. 0 Individual Rx masking and queue feature are disabled. 1 Individual Rx masking and queue feature are enabled. 16–17 Reserved PXR40 Microcontroller Reference Manual, Rev. 1 24-16 Freescale Semiconductor...
Page 827 One full ID (standard or extended) per filter element. Two full standard IDs or two partial 14-bit extended IDs per filter element. Four partial 8-bit IDs (standard or extended) per filter element. All frames rejected. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-17...
Page 828: Control Register (Flexcan_X_Ctrl)
Phase Buffer Segment 2 = (PSEG2 + 1) x Time-Quanta. Bus Off Mask BOFF_MS This bit provides a mask for the Bus Off Interrupt. 0 Bus Off interrupt disabled 1 Bus Off interrupt enabled PXR40 Microcontroller Reference Manual, Rev. 1 24-18 Freescale Semiconductor...
Page 829 0 Just one sample is used to determine the bit value 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-19...
Page 830 This 3-bit field defines the length of the Propagation Segment in the bit time. The valid programmable values are 0–7. Propagation Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period. NOTES: One time quantum is equal to the Sclock period. PXR40 Microcontroller Reference Manual, Rev. 1 24-20 Freescale Semiconductor...
Page 831: Free Running Timer (Flexcan_X_Timer)
If desired, software can poll the register to discover when the data was actually written. Base + 0x0008 RESET: TIMER RESET: = Unimplemented or Reserved Figure 24-7. Free Running Timer (FLEXCAN_x_TIMER) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-21...
Page 832: Rx Global Mask (Flexcan_X_Rxgmask)
ID filter table. This register has the same structure as the Rx Global Mask Register. It must be programmed while the module is in Freeze Mode, and must not be modified when the module is transmitting or receiving frames. • Address Offset: 0x14 • Reset Value: 0xFFFF_FFFF PXR40 Microcontroller Reference Manual, Rev. 1 24-22 Freescale Semiconductor...
Page 833: Rx 15 Mask (Flexcan_X_Rx15Mask)
128, the FLT_CONF field in the Error and Status Register is updated to be ‘Error Active’ and both error counters are reset to zero. At any instance of dominant bit following PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-23...
Page 834 119 and 127 to resume to ‘Error Active’ state. Base + 0x001C RESET: Rx_Err_Counter Tx_Err_Counter RESET: = Unimplemented or Reserved Figure 24-9. Error Counter Register (FLEXCAN_x_ECR) PXR40 Microcontroller Reference Manual, Rev. 1 24-24 Freescale Semiconductor...
Page 835: Error And Status Register (Flexcan_X_Esr)
Base + 0x0020 TWRN RWRN _INT _INT RESET: BIT1_ BIT0_ ACK_ CRC_ FRM_ STF_ TX_W IDLE TXRX FLT_CONF BOFF ERR_ _INT RESET: = Unimplemented or Reserved Figure 24-10. Error and Status Register PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-25...
Page 836 1 A Stuffing Error occurred since last read of this register. TX Error Counter TX_WRN This bit indicates when repetitive errors are occurring during message transmission. 0 No such occurrence 1 TX_Err_Counter  96 PXR40 Microcontroller Reference Manual, Rev. 1 24-26 Freescale Semiconductor...
Page 837 Register (ERR_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’.Writing ‘0’ has no effect. 0 No such occurrence 1 Indicates setting of any Error Bit in the Error and Status Register Reserved PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-27...
Page 838: Interrupt Masks 2 Register (Flexcan_X_Imask2)
CPU to determine which buffer generates an interrupt after a successful transmission or reception (i.e., when the corresponding FLEXCAN_x_IFLAG1 bit is set). Base + 0x0028 RESET: RESET: Figure 24-12. Interrupt Masks 1 Register (FLEXCAN_x_IMASK1) PXR40 Microcontroller Reference Manual, Rev. 1 24-28 Freescale Semiconductor...
Page 839: Interrupt Flags 2 Register (Flexcan_X_Iflag2)
Buffer MB Interrupt BUF32I– Each bit flags the respective FlexCAN Message Buffer (MB32 to MB63) interrupt. BUF63I 0 No such occurrence 1 The corresponding buffer has successfully completed transmission or reception PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-29...
Page 840: Interrupt Flags 1 Register (Flexcan_X_Iflag1)
Buffer MB Interrupt BUF31I– Each bit flags the respective FlexCAN Message Buffer (MB8 to MB31) interrupt. BUF8I 0 No such occurrence 1 The corresponding MB has successfully completed transmission or reception PXR40 Microcontroller Reference Manual, Rev. 1 24-30 Freescale Semiconductor...
Page 841 If the FIFO is not enabled, these bits flag the interrupts for MB0 to MB4. If the FIFO is enabled, these flags are not UF0I used and must be considered as reserved locations. 0 No such occurrence 1 Corresponding MB completed transmission/reception PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-31...
Page 842: Rx Individual Mask Registers (Rximr0–Rximr63)
ID field. A masking scheme makes it possible to match the ID programmed on the MB with a range of IDs on received CAN frames. For transmission, an arbitration algorithm decides the PXR40 Microcontroller Reference Manual, Rev. 1 24-32 Freescale Semiconductor...
Page 843: Transmit Process
Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the same positions they are transmitted in the CAN frame. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-33...
Page 844: Receive Process
Once the MB is activated in the third step, it will be able to receive frames that match the programmed ID. At the end of a successful reception, the MB is updated by the MBM as follows: PXR40 Microcontroller Reference Manual, Rev. 1 24-34 Freescale Semiconductor...
Page 845 Read the Control and Status word (optional – needed only if a mask was used for IDE and RTR bits) • Read the ID field (optional – needed only if a mask was used) • Read the Data field PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-35...
Page 846: Matching Process
The matching algorithm described above can be changed to be the same one used in previous versions of the FlexCAN module. When the MBFEN bit in FLEXCAN_x_MCR is negated, the matching algorithm PXR40 Microcontroller Reference Manual, Rev. 1 24-36 Freescale Semiconductor...
Page 847: Data Coherence
MB is updated and no interrupt flag is set. In this way the CPU just needs to read the abort code to make sure the active MB was deactivated. Although the AEN bit is asserted and the CPU PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-37...
Page 848: Message Buffer Deactivation
There is a point in time until which the deactivation of a Tx MB causes it not to be transmitted (end of move-out). After this point, it is transmitted but no interrupt is issued and the Code field is not PXR40 Microcontroller Reference Manual, Rev. 1 24-38 Freescale Semiconductor...
Page 849: Message Buffer Lock Mechanism
FIFO feature. When the FIFO is enabled, the memory region normally occupied by the first In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior will be honoured when the MBFEN bit is negated. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-39...
Page 850: Precautions When Using Global Mask And Individual Mask Registers
Precautions when using Global Mask and Individual Mask registers Mask filtering alignment is affected based on the setting of the FEN and BCC of MCR. Table 24-18 table shows recommended actions depending on FEN and BCC settings. PXR40 Microcontroller Reference Manual, Rev. 1 24-40 Freescale Semiconductor...
Page 851: Can Protocol Related Features
The data length of this frame is independent of the DLC field in the remote frame that initiated its transmission. 24.4.8.2 Overload Frames FlexCAN does transmit overload frames due to detection of following conditions on CAN bus: • Detection of a dominant bit in the first/second bit of Intermission PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-41...
Page 852: Time Stamp
‘time quantum’ used to compose the CAN waveform. A time quantum is the atomic unit of time handled by the CAN engine. CANCLK -------------------------------------------------------   Prescaler Þ alue A bit time is subdivided into three segments (reference Figure 24-17 Table 24-19): PXR40 Microcontroller Reference Manual, Rev. 1 24-42 Freescale Semiconductor...
Page 853 CAN compliant segment settings and the related parameter values. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-43...
Page 854: Arbitration And Matching Timing
• There must be a minimum ratio between the peripheral clock frequency and the CAN bit rate, as specified in Table 24-21 PXR40 Microcontroller Reference Manual, Rev. 1 24-44 Freescale Semiconductor...
Page 855: Modes Of Operation Details
The MCU is removed from Debug Mode and/or the HALT bit is negated Once out of Freeze Mode, FlexCAN tries to re-synchronize to the CAN bus by waiting for 11 consecutive recessive bits. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-45...
Page 856: Module Disable Mode
Tx and Rx interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission or reception. Each of the buffers has assigned a flag bit in the IFLAG PXR40 Microcontroller Reference Manual, Rev. 1 24-46 Freescale Semiconductor...
Page 857: Bus Interface
Mask Registers space would be from 0x0884 to 0x097F. NOTE Unused MB space must not be used as general purpose RAM while FlexCAN is transmitting and receiving CAN frames. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-47...
Page 858: Initialization/Application Information
Initialize the Control Register – Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW – Determine the bit rate by programming the PRESDIV field – Determine the internal arbitration mode (LBUF bit) PXR40 Microcontroller Reference Manual, Rev. 1 24-48 Freescale Semiconductor...
Page 859: Flexcan Addressing And Ram Size Configurations
MAXMB field in the FLEXCAN_x_MCR Register. For 16 MB configuration, MAXMB can be any number between 0–15.For 32 MB configuration, MAXMB can be any number between 0–31.For 64 MB configuration, MAXMB can be any number between 0 – PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 24-49...
Page 860 FlexCAN Module PXR40 Microcontroller Reference Manual, Rev. 1 24-50 Freescale Semiconductor...
Page 861: Introduction
Figure 25-1. DSPI Block Diagram NOTE The TXSS signal is described on Section 25.3.2.1, DSPI Module Configuration Register (DSPI_MCR). For details on 32 bits operation see Section 25.4.9, Timed Serial Bus (TSB). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-1...
Page 862: Overview
Buffered receive operation using the RX FIFO (depth of 4 entries) • TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues • Visibility into TX and RX FIFOs for ease of debugging PXR40 Microcontroller Reference Manual, Rev. 1 25-2 Freescale Semiconductor...
Page 863 Pin serialization/deserialization with interleaved SPI frames for control and diagnostics • Continuous serial communications clock • Enhanced DSI logic to implement a 32 bits Timed Serial Bus (TSB) configuration, supporting the Micro Second Bus downstream frame format. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-3...
Page 864: Dspi Configurations
In the DSI Configuration the DSPI serializes up to 16 Parallel Input signals or register bits. The DSPI also deserializes the received data to Parallel Output signals or to a memory-mapped register. The data is transferred using a SPI-like protocol. PXR40 Microcontroller Reference Manual, Rev. 1 25-4 Freescale Semiconductor...
Page 865: Csi Configuration
When a request is made to enter External Stop Mode, the DSPI block acknowledges the request and completes the transfer in progress. When the DSPI reaches the frame boundary it signals that the system clocks to the DSPI block may be shut off. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-5...
Page 866: Debug Mode
25.2.2.2 PCS[1] - PCS[3] — Peripheral Chip Selects 1 - 3 PCS[1] - PCS[3] are Peripheral Chip Select output signals in Master Mode. In Slave Mode these signals are not used. PXR40 Microcontroller Reference Manual, Rev. 1 25-6 Freescale Semiconductor...
Page 867: Pcs[4]/Mtrig — Peripheral Chip Select 4/Master Trigger
In Master Mode while in DSI or CSI Configurations, the HT signal initiates a data transfer when the TRRE bit in the DSPI_DSICR is set and a rising or falling edge is detected on HT. Which edge to trigger on is determined by the TPOL bit in the DSPI_DSICR. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-7...
Page 868: Memory Map And Register Definition
DSPI_RXFR0—DSPI Receive FIFO Register 0 - 0x0000_0000 25.3.2.9/25 DSPI_RXFR3—DSPI Receive FIFO Register 3 DSPI_BASE+0x88 DSPI_BASE+0x8C Reserved DSPI_BASE+0xB8 DSI Registers DSPI_BASE+0xBC DSPI_DSICR—DSPI DSI Configuration Register 0x0000_0000 25.3.2.10/25 DSPI_BASE+0xC0 DSPI_SDR—DSPI DSI Serialization Data Register 0x0000_0000 25.3.2.11/27 PXR40 Microcontroller Reference Manual, Rev. 1 25-8 Freescale Semiconductor...
Page 869: Register Descriptions
Only the HALT and MDIS bits in the DSPI_MCR may be changed while the DSPI is in the Running state. Address: DSPI_BASE Access: R/W MSTR DCONF Reset DOZE MDIS SMPL_PT HALT Reset Figure 25-3. DSPI Module Configuration Register (DSPI_MCR) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-9...
Page 870 1 The inactive state of PCSx is high Doze Enable. The DOZE bit provides support for externally controlled Doze Mode power-saving DOZE mechanism. See Section 25.4.11, Power Saving Features, for details. PXR40 Microcontroller Reference Manual, Rev. 1 25-10 Freescale Semiconductor...
Page 871: Dspi Transfer Count Register (Dspi_Tcr)
The DSPI_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter is intended to assist in queue management. The user must not write to the DSPI_TCR while the DSPI is in the Running state. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-11...
Page 872: Dspi Clock And Transfer Attributes Registers 0–7 (Dspi_Ctar0–Dspi_Ctar7)
In CSI Configuration, the transfer attributes are selected based on whether the current frame is SPI data or DSI data. SPI transfers in CSI Configuration follow the protocol described for SPI Configuration, and DSI transfers in CSI Configuration follow the protocol described for DSI Configuration. CSI Configuration is PXR40 Microcontroller Reference Manual, Rev. 1 25-12 Freescale Semiconductor...
Page 873 PDT and DT delays are valid. Address: DSPI_BASE + 0xC–DSPI_BASE + 0x28 Access: R/W FMSZ CPHA LSBFE PCSSCK PASC Reset CSSCK Reset Figure 25-5. DSPI Clock and Transfer Attributes Register 0–7 (DSPI_CTAR0–DSPI_CTAR7) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-13...
Page 874 PCS and the first edge of the SCK. This field is only used in Master Mode. The table below lists the prescaler values. See the CSSCK[0:3] field description for details on how to compute the PCS to SCK Delay. PCSSCK PCS to SCK Delay Prescaler Value PXR40 Microcontroller Reference Manual, Rev. 1 25-14 Freescale Semiconductor...
Page 875 The Baud Rate Prescaler values are listed in the table below. See the BR[0:3] field description for details on how to compute the baud rate. Baud Rate Prescaler Value PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-15...
Page 876 Eqn. 25-4 --------------- -------------------- - SCK baud rate Section 25.4.6.1, Baud Rate Generator, for more details. Table 25-8. DSPI SCK Duty Cycle CPHA SCK Duty Cycle 50/50 50/50 33/66 40/60 43/57 PXR40 Microcontroller Reference Manual, Rev. 1 25-16 Freescale Semiconductor...
Page 877 0111 1111 65536 Table 25-11. DSPI After SCK Delay Scaler After SCK Delay After SCK Delay Scaler Value Scaler Value 0000 1000 0001 1001 1024 0010 1010 2048 0011 1011 4096 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-17...
Page 878: Dspi Status Register (Dspi_Sr)
DSPI_SR by writing a ‘1’ to it. Writing a ‘0’ to a flag bit has no effect. This register may not be writable in MDIS Mode due to the use of power saving mechanisms. PXR40 Microcontroller Reference Manual, Rev. 1 25-18 Freescale Semiconductor...
Page 879 DMA controller when the TX FIFO is full. 0 TX FIFO is full 1 TX FIFO is not full 7–11 Reserved, should be cleared. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-19...
Page 880: Dspi Dma/Interrupt Request Select And Enable Register (Dspi_Rser)
The DSPI_RSER also selects the type of request to be generated. See the individual bit descriptions for information on the types of requests the bits support. The user must not write to the DSPI_RSER while the DSPI is in the Running state. PXR40 Microcontroller Reference Manual, Rev. 1 25-20 Freescale Semiconductor...
Page 881 TFFF_RE bit in the DSPI_RSER register is set, this bit selects between generating an interrupt request or a DMA request. 0 Interrupt request will be generated 1 DMA request will be generated 8–11 Reserved, should be cleared. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-21...
Page 882: Dspi Push Tx Fifo Register (Dspi_Pushr)
Eight or sixteen bit write accesses to the DSPI_PUSHR will transfer 32 bits to the TX FIFO. Address: DSPI_BASE + 0x34 Access: R/W R CON CTCN CTAS Reset TXDATA Reset Figure 25-8. DSPI PUSH TX FIFO Register (DSPI_PUSHR) PXR40 Microcontroller Reference Manual, Rev. 1 25-22 Freescale Semiconductor...
Page 883: Dspi Pop Rx Fifo Register (Dspi_Popr)
(RX FIFO) Buffering Mechanism, for a description of the RX FIFO operations. Eight or sixteen bit read accesses to the DSPI_POPR will read from the RX FIFO and update the counter and pointer. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-23...
Page 884: Dspi Transmit Fifo Registers 0–3 (Dspi_Txfr0–Dspi_Txfr3)
DSPI_TXFRx registers does not alter the state of the TX FIFO. The number of registers used to implement the TX FIFO is four for this device Address: DSPI_BASE+0x3C–DSPI_BASE+0x78 Access: Read Only TXCMD Reset TXDATA Reset Figure 25-10. DSPI Transmit FIFO Register 0–15 (DSPI_TXFR0–DSPI_TXFR15) PXR40 Microcontroller Reference Manual, Rev. 1 25-24 Freescale Semiconductor...
Page 885: Dspi Receive Fifo Registers 0–3 (Dspi_Rxfr0–Dspi_Rxfr3)
25.3.2.10 DSPI DSI Configuration Register (DSPI_DSICR) The DSI Configuration Register selects various attributes associated with DSI and CSI Configurations. The user must not write to the DSPI_DSICR while the DSPI is in the Running state. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-25...
Page 886 Control, for more information. When TSBC bit is set, bits TPOL bit is used for both DSICR and DSICR1 registers. 0 Falling edge will initiate a transfer 1 Rising edge will initiate a transfer PXR40 Microcontroller Reference Manual, Rev. 1 25-26 Freescale Semiconductor...
Page 887: Dspi Dsi Serialization Data Register (Dspi_Sdr)
DSPI_SDR on the rising edge of every system clock. The DSPI_SDR is read-only. When the TXSS bit in the DSPI_DSICR is negated, the data in the DSPI_SDR is the source of the serialized data. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-27...
Page 888: Dspi Dsi Alternate Serialization Data Register (Dspi_Asdr)
The DSPI_ASDR is a 32 bits register, the upper 16 bits are only used, when TSB is enabled. For non TSB configurations only the least 16 significant bits are used. Address: DSPI_BASE + 0xC4 Access: R/W ASER_DATA Reset ASER_DATA Reset Figure 25-14. DSPI DSI Alternate Serialization Data Register (DSPI_ASDR) PXR40 Microcontroller Reference Manual, Rev. 1 25-28 Freescale Semiconductor...
Page 889: Dspi Dsi Transmit Comparison Register (Dspi_Compr)
The DSPI_DDR register holds the signal states for the Parallel Output signals. The DSPI_DDR is read-only and it is memory mapped so that host software can read the incoming DSI frames. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-29...
Page 890: Dspi Dsi Configuration Register 1 (Dspi_Dsicr1)
DSPI_DSICR1 while the DSPI is in the Running state. If TSB configuration is not used the register value is ignored. Address: DSPI_BASE + 0xD0 Access: R/W TSBCNT Reset Reset Figure 25-17. DSPI DSI Configuration Register 1 (DSPI_DSICR1) PXR40 Microcontroller Reference Manual, Rev. 1 25-30 Freescale Semiconductor...
Page 891: Functional Description
MCUs and peripheral devices. The DSPI can also be used to reduce the number of pins required for I/O by serializing and deserializing up to 16 Parallel Input/Output signals. All PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-31...
Page 892 Formats. The transfer rate and delay settings are described in Section 25.4.6, DSPI Baud Rate and Clock Delay Generation. Section 25.4.11, Power Saving Features, for information on the power-saving features of the DSPI. PXR40 Microcontroller Reference Manual, Rev. 1 25-32 Freescale Semiconductor...
Page 893: Modes Of Operation
SS asserted. In Slave Mode the SCK is provided by the bus master. All transfer attributes are controlled by the bus master but clock polarity, clock phase and numbers of bits to transfer must still be configured in the DSPI slave for proper communications. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-33...
Page 894: Module Disable Mode
The TXRXS bit in the DSPI_SR is asserted in the RUNNING state. Figure 25-19 shows a state diagram of the start and stop mechanism. The transitions are described in Table 25-26. PXR40 Microcontroller Reference Manual, Rev. 1 25-34 Freescale Semiconductor...
Page 895: Serial Peripheral Interface (Spi) Configuration
Master Mode and Slave Mode. The main difference is that in Master Mode the DSPI initiates and controls the transfer according to the fields in the SPI command field of the TX FIFO PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-35...
Page 896: Master Mode
TX FIFO. The TXNXTPTR field indicates which TX FIFO Entry will be transmitted during the next transfer. The TXNXTPTR contains the positive offset from DSPI_TXFR0 in number of 32-bit registers. For example, PXR40 Microcontroller Reference Manual, Rev. 1 25-36 Freescale Semiconductor...
Page 897: Receive First In First Out (Rx Fifo) Buffering Mechanism
32-bit registers. For example, POPNXTPTR equal to two means that the DSPI_RXFR2 contains the received SPI data that will be returned when DSPI_POPR is read. The POPNXTPTR field is incremented every time the DSPI_POPR is read. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-37...
Page 898: Deserial Serial Interface (Dsi) Configuration
In DSI Master Mode the DSPI initiates and controls the DSI transfers. The DSI Master has four different conditions that can initiate a transfer: • Continuous • Change in data • Trigger signal PXR40 Microcontroller Reference Manual, Rev. 1 25-38 Freescale Semiconductor...
Page 899: Dsi Slave Mode
Slave Bus Interface DSPI Alternate DSI Config. DSI Transmit Register Serialization Data Register Comparison Register Clock DSI Serialization Logic Data Register Parallel SOUT Inputs Shift Register Control Logic Figure 25-20. DSI Serialization Diagram PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-39...
Page 900: Dsi Deserialization
DSPI_COMPR. When the data in the DSPI_SDR or the DSPI_ASDR is different from the data in the DSPI_COMPR a new DSI frame is transmitted. The TXSS bit in the DSPI_DSICR selects which register PXR40 Microcontroller Reference Manual, Rev. 1 25-40 Freescale Semiconductor...
Page 901: Multiple Transfer Operation (Mto)
This requires setting SIU_DISR_SINSELx bits of the first slave DSPI to “00” and configuring the first slave's SIN pin and master SOUT pin as DSPI SIN and DSPI SOUT, respectively. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-41...
Page 902 The serial chaining allows transfers of DSI frames of up to a total of 64 bits, using transfers of smaller DSI frames concatenated together by multiple DSPIs. Figure 25-23 shows an example of how the blocks can be connected in a device. PXR40 Microcontroller Reference Manual, Rev. 1 25-42 Freescale Semiconductor...
Page 903: Combined Serial Interface (Csi) Configuration
The DSPI is in CSI Configuration when the DCONF field in the DSPI_MCR is 0b10. Figure 25-24 shows an example PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-43...
Page 904: Csi Serialization
SPI frames are determined by the DSPI_CTAR register selected by the CTAS field in the SPI command halfword. The transfer attributes for the DSI frames are determined by the DSPI_CTAR register selected by the DSICTAS field in the DSPI_DSICR. Figure 25-25 shows the CSI Serialization logic. PXR40 Microcontroller Reference Manual, Rev. 1 25-44 Freescale Semiconductor...
Page 905: Csi Deserialization
Figure 25-26 shows the CSI Deserialization logic. Slave Bus Interface RX FIFO Control Transfer Logic Priority Logic DSI Deserialization Data Register Parallel Outputs Shift Register (P_OUT) Figure 25-26. CSI Deserialization Diagram PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-45...
Page 906: Dspi Baud Rate And Clock Delay Generation
After SCK delay. Table 25-30. After SCK Delay Computation Example PASC Prescaler Scaler After SCK Delay periph 0.96 s 0b01 0b0100 100 MHz PXR40 Microcontroller Reference Manual, Rev. 1 25-46 Freescale Semiconductor...
Page 907 Table 25-32. Delay after Transfer Computation Example in TSB Configuration PDT field (Tsck) 1280 1792 1536 2560 3584 1024 3072 5120 7168 2048 6144 10240 14336 4096 12288 20480 28672 8192 24576 40960 57344 16384 49152 81920 114688 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-47...
Page 908: Peripheral Chip Select Strobe Enable (Pcss)
Table 25-34. Peripheral Chip Select Strobe Negate Computation Example PASC Prescaler Delay after Transfer periph 0b11 100 MHz 70.0 ns The PCSS signal is not supported when Continuous Serial Communication SCK is enabled (CONT_SCKE=1). PXR40 Microcontroller Reference Manual, Rev. 1 25-48 Freescale Semiconductor...
Page 909: Transfer Formats
In this format, the master and slave sample their SIN pins on the odd-numbered SCK edges and change the data on their SOUT pins on the even-numbered SCK edges. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-49...
Page 910: Classic Spi Transfer Format (Cpha = 1)
SCK edge before the first data bit becomes available on the slave SOUT pin. In this format the master and slave devices change the data on their SOUT pins on the odd-numbered SCK edges and sample the data on their SIN pins on the even-numbered SCK edges PXR40 Microcontroller Reference Manual, Rev. 1 25-50 Freescale Semiconductor...
Page 911: Modified Spi/Dsi Transfer Format (Mtfe = 1, Cpha = 0)
SCK delay has elapsed the first SCK edge is generated. The Slave samples the Master SOUT signal on every odd numbered SCK edge. The Slave also places new data on the Slave SOUT on every odd numbered clock edge. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-51...
Page 912: Modified Spi/Dsi Transfer Format (Mtfe = 1, Cpha = 1)
SCK. No clock edge will be visible on the Master SCK pin during the sampling of the last bit. The SCK to PCS delay must be greater or equal to half of the SCK period. PXR40 Microcontroller Reference Manual, Rev. 1 25-52 Freescale Semiconductor...
Page 913: Continuous Selection Format
The idle states of the Chip Select signals are selected by the PCSIS field in the DSPI_MCR. Figure 25-33 shows the timing diagram for two four-bit transfers with CPHA = 1 and CONT = 0. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-53...
Page 914 Switching CTAR registers or changing which PCS signals are asserted between frames while using Continuous Selection can cause errors in the transfer. The PCS signal should be negated before CTAR is switched or different PCS signals are selected. PXR40 Microcontroller Reference Manual, Rev. 1 25-54 Freescale Semiconductor...
Page 915: Continuous Serial Communications Clock
1xT cycles by configuring PDT and DT values in the respective CTAR register. Figure 25-35 shows timing diagram for Continuous SCK format with Continuous Selection disabled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-55...
Page 916: Timed Serial Bus (Tsb)
Timed Serial Bus (TSB) The DSPI can be programmed in Timed Serial Bus configuration by asserting the TSBC bit in the DSPI_DSICR register, see Section 25.3.2.10, DSPI DSI Configuration Register (DSPI_DSICR), for PXR40 Microcontroller Reference Manual, Rev. 1 25-56 Freescale Semiconductor...
Page 917 TSCK and the PDT and DT fields of the specific DSPI_CTAR0-7 register select the delay after transfer. Some values will not be possible, see the reference manual for details. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-57...
Page 918: Pcs Switch Over Timing
CSC and ASC delay fields respectively when not in Continuous SCK mode. PXR40 Microcontroller Reference Manual, Rev. 1 25-58 Freescale Semiconductor...
Page 919: Tsb Command Frame Format
25-40. A data frame with a selection bit always starts with a low level bit at SOUT. The number of data bits in the active phase is from 4 to 32 bits, and the least significant bit of a data portion is transmitted first (LSBFE = 1). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-59...
Page 920: Interrupts/Dma Requests
The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit FIFO Fill Request is generated when the number of entries in the TX FIFO is less than the maximum number of possible entries, PXR40 Microcontroller Reference Manual, Rev. 1 25-60 Freescale Semiconductor...
Page 921: Transfer Complete Interrupt Request
All power saving features require logic external to the DSPI. Figure 25-41 shows an example on how the DSPI power saving features can be used in a device. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-61...
Page 922: Stop Mode (External Stop Mode)
DSPI is in the Module Disable Mode. Reading the RX FIFO Pop Register will not change the state of the RX FIFO. Likewise, writing to the TX FIFO Push Register will not change the state of the PXR40 Microcontroller Reference Manual, Rev. 1 25-62 Freescale Semiconductor...
Page 923: Slave Bus Signal Gating
10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit. 11. Enable serial transmission and serial reception of data by clearing the EOQF bit. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-63...
Page 924: Baud Rate Settings
DSPI_CTAR registers. The values calculated assume a 100 MHz system frequency. This table does not apply for TSB Continuous Mode. PXR40 Microcontroller Reference Manual, Rev. 1 25-64 Freescale Semiconductor...
Page 925: Calculation Of Fifo Pointer Addresses
FIFO Counter. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO. Section 25.4.3.4, Transmit First In First Out (TX FIFO) Buffering Mechanism, and Section 25.4.3.5, Receive First In First Out (RX FIFO) Buffering Mechanism, for details on the FIFO operation. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-65...
Page 926: Address Calculation For The First-In Entry And Last-In Entry In The Tx Fifo
The memory address of the last-in entry in the RX FIFO is computed by the following equation:    Eqn. 25-10 Last-in Entry address RX FIFO Base modulo RX FIFO depth RXCTR POPNXTPTR 1 – RX FIFO Base - Base address of RX FIFO PXR40 Microcontroller Reference Manual, Rev. 1 25-66 Freescale Semiconductor...
Page 927 Deserial Serial Peripheral Interface (DSPI) RXCTR - RX FIFO counter POPNXTPTR - Pop Next Pointer RX FIFO Depth - Receive FIFO depth, implementation specific PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 25-67...
Page 928 Deserial Serial Peripheral Interface (DSPI) PXR40 Microcontroller Reference Manual, Rev. 1 25-68 Freescale Semiconductor...
Page 929: Bibliography
26.1.3 Glossary Table 26-2. Glossary Term Definition Logic level one The voltage that corresponds to Boolean true (1) state. Logic level zero The voltage that corresponds to Boolean false (0) state. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-1...
Page 930: Overview
A LIN frame with the header field transmitted by the eSCI module and the data byte fields and checksum field received by the eSCI module 26.1.4 Overview The eSCI block allows asynchronous serial communications with peripheral devices and other CPUs. It includes special support to interface to LIN slave devices. PXR40 Microcontroller Reference Manual, Rev. 1 26-2 Freescale Semiconductor...
Page 931: Features
Separately enabled transmitter and receiver • Two receiver wake up methods: — Idle line wake-up — Address mark wake-up • Interrupt-driven operation with eight flags: — Transmitter empty — Transmission complete — Receiver full PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-3...
Page 932: Modes Of Operation
In the Disabled mode the eSCI module indicates to the clocking system, that all module clocks can be turned off. The eSCI module is in the Disabled Mode, if the MDIS bit in the Control Register 2 (eSCI_CR2) is set. PXR40 Microcontroller Reference Manual, Rev. 1 26-4 Freescale Semiconductor...
Page 933: Stop Mode
After the end of the transmission, all pending transfer requests are cleared and no more data will be transmitted. None of the transmitter related register flags will be set. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-5...
Page 934: Detailed Signal Descriptions
Baud Rate Register (eSCI_BRR) Control Register 1 (eSCI_CR1) 0x0004 Control Register 2 (eSCI_CR2) SCI Data Register (ESCI_DR) 0x0008 Interrupt Flag and Status Register 1 (eSCI_IFSR1) Interrupt Flag and Status Register 2 (eSCI_IFSR2) PXR40 Microcontroller Reference Manual, Rev. 1 26-6 Freescale Semiconductor...
Page 935: Register Descriptions
Writes to a reserved register location do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-7...
Page 936: Baud Rate Register (Esci_Brr)
This register provides bits to configure the functionality of the module, provides the interrupt enable bits for the interrupt flags provided in Interrupt Flag and Status Register 1 (eSCI_IFSR1) and provides the control bits for the transmitter and receiver. PXR40 Microcontroller Reference Manual, Rev. 1 26-8 Freescale Semiconductor...
Page 937 1 Transmitter enabled. Receiver Enable.This control bit enables and disables the receiver. The control features of the receiver are described in Section 26.4.5.3.1, Receiver States and Transitions. 0 Receiver disabled. 1 Receiver enabled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-9...
Page 938: Control Register 2 (Esci_Cr2)
0 Standard Bit error detection performed as described in Section 26.4.6.5.3, Standard Bit Error Detection. 1 Fast Bit error detection performed as described in Section 26.4.6.5.4, Fast Bit Error Detection. Note: This bit is used in LIN mode only. PXR40 Microcontroller Reference Manual, Rev. 1 26-10 Freescale Semiconductor...
Page 939 0 OR interrupt request generation disabled. 1 OR interrupt request generation enabled. NFIE Noise Interrupt Enable. This bit controls the eSCI_IFSR1[NF] interrupt request generation. 0 NF interrupt request generation disabled. 1 NF interrupt request generation enabled. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-11...
Page 940: Sci Data Register (Esci_Dr)
(ESCI_DR). In case of an overrun error for subsequent frames this bit is set too. 0 None of the selected errors occured. 1 At least one of the selected errors occured. PXR40 Microcontroller Reference Manual, Rev. 1 26-12 Freescale Semiconductor...
Page 941: Interrupt Flag And Status Register 1 (Esci_Ifsr1)
Idle Line Interrupt Flag. This interrupt flag is set when an idle character was detected and the receiver is not in the wakeup state. Note: This flag is set in SCI mode only. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-13...
Page 942: Interrupt Flag And Status Register 2 (Esci_Ifsr2)
This register provides interrupt flags that indicate the occurrence of LIN related events. The related interrupt enable bits are located in LIN Control Register 1 (eSCI_LCR1) LIN Control Register 2 (eSCI_LCR2). All interrupt flags in this register will be set in LIN mode only. PXR40 Microcontroller Reference Manual, Rev. 1 26-14 Freescale Semiconductor...
Page 943: Lin Control Register 1 (Esci_Lcr1)
This register provides control bits to control and configure the LIN hardware. This register provides the interrupt enable bits for the interrupt flags in Interrupt Flag and Status Register 2 (eSCI_IFSR2). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-15...
Page 944 1 CKERR interrupt request generation enabled. FCIE Frame Complete Interrupt Enable. This bit controls the eSCI_IFSR2[FRC] interrupt request generation. 0 FRC interrupt request generation disabled. 1 FRC interrupt request generation enabled. PXR40 Microcontroller Reference Manual, Rev. 1 26-16 Freescale Semiconductor...
Page 945: Lin Control Register 2 (Esci_Lcr2)
This register is used by the application to initiate the LIN frame header generation for both LIN TX frames and LIN RX frames. If a LIN TX frame is generated, this register is used to provide the payload data for the LIN TX frame. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-17...
Page 946 RX frame: Defines the time available for a complete RX frame transfer, as described in Section 26.4.6.5.4, Fast Bit Error Detection. TX frame: Must be set to 0. Transmit Data. Data bits for transmission. PXR40 Microcontroller Reference Manual, Rev. 1 26-18 Freescale Semiconductor...
Page 947: Lin Receive Register (Esci_Lrr)
SYNM EROE ERFE ERPE Reset Figure 26-14. Control Register 3 (eSCI_CR3) This register is used to control the frame formats and the generation of the ERR bit in the SCI Data Register (ESCI_DR). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-19...
Page 948 Frame Format Mode 2. This control bit together with the M bit of the Control Register 1 (eSCI_CR1) controls the frame format used. The supported frame formats and the related settings are defines in Section 26.4.2, Frame Formats. PXR40 Microcontroller Reference Manual, Rev. 1 26-20 Freescale Semiconductor...
Page 949: Functional Description
LIN byte fields (Figure 26-15) SCI Frames (8 payload bits)(Figure 26-16) SCI Frames (9 payload bits) (Figure 26-17) The address bit identifies the frame as an address character. See Section 26.4.5.5, Multiprocessor Communication. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-21...
Page 950 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 START PARITY STOP STOP BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT9 BIT10 BIT11 Figure 26-18. SCI Frame Formats (2 stop bits) PXR40 Microcontroller Reference Manual, Rev. 1 26-22 Freescale Semiconductor...
Page 951: Break Character Formats
BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT9 BIT10 BIT11 Delemit Figure 26-20. LIN Break Symbol Format The structure and content of the SCI break characters is shown in Figure 26-21. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-23...
Page 952: Idle Character Formats
The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. PXR40 Microcontroller Reference Manual, Rev. 1 26-24 Freescale Semiconductor...
Page 953: Module Clock
The baud rate generator is controlled by the value of the SBR field in the Baud Rate Register (eSCI_BRR). The frequency of the receiver sample clock is determined by Equation 26-2. MCLK -------------- - Eqn. 26-2 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-25...
Page 954: Baud Rate Tolerance
To ensure error free reception of the stop bit, the transmitter must start the transmission of the stop bit before the receiver samples RSC8.  Eqn. 26-5 STOP STOP PXR40 Microcontroller Reference Manual, Rev. 1 26-26 Freescale Semiconductor...
Page 955: Slower Receiver Tolerance
To ensure error free reception of the last stop bit, the transmitter must start the transmission of the start bit after the receiver samples RS10.  Eqn. 26-9 STOP START PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-27...
Page 956: Sci Mode
The transmitter has four basic states which are shown and described in Table 26-25. The state transitions that can triggered by the application commands are shown in Table 26-26. The state transitions that can PXR40 Microcontroller Reference Manual, Rev. 1 26-28 Freescale Semiconductor...
Page 957 TACT in the Interrupt Flag and Status Register 1 (eSCI_IFSR1), the TDRE, and the TC flag in the Interrupt Flag and Status Register 1 (eSCI_IFSR1) changed as a action result of the transition. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-29...
Page 958 Idle state via the halt transition. The transfer complete flag TC in Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set and the internal commit bit iCMT is cleared. PXR40 Microcontroller Reference Manual, Rev. 1 26-30 Freescale Semiconductor...
Page 959 The transmission of a preamble is started when the transmitter is in Ready state, the internal iPRE bit, which is not visible to the application, is set, and the SBK in the Control Register 1 (eSCI_CR1) is clear. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-31...
Page 960: Receiver
Table 26-26. The state transitions that can triggered by the module are shown in Table 26-27. The state diagram of the transmitter is shown in Figure 26-25. PXR40 Microcontroller Reference Manual, Rev. 1 26-32 Freescale Semiconductor...
Page 961 Receiver is enabled by application command. RE:=0 RE=1 Receiver is disabled by application command RWU:=1 RE=1 Receiver is set into wakeup mode The module transition shown in Table 26-31 are triggered when the described event occurs. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-33...
Page 962 In Single Wire Mode, the RXD pin is disconnected from the eSCI module and the TXD pin is used for both receiving and transmitting. RECEIVER TRANSMITTER Figure 26-29. Single Wire Mode PXR40 Microcontroller Reference Manual, Rev. 1 26-34 Freescale Semiconductor...
Page 963 Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set. If the receive interrupt enable bit RIE in the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set, the RDRF interrupt request is generated. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-35...
Page 964 3. Setup the DMA controller channel. System Memory DATA 1 DATA 2 eSCI Controller RX DMA channel DATA N DATA 1 DATA N SCI Data frame Figure 26-31. DMA Controlled SCI Data Frame Reception PXR40 Microcontroller Reference Manual, Rev. 1 26-36 Freescale Semiconductor...
Page 965 Section 26.4.5.3.15, Start Bit Sampling. Additionally, the synchronization of the cyclic sample counter RSC can be configured to be performed during data bit reception as described in Section 26.4.5.3.17, Data Bit Synchronization. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-37...
Page 966 RS8, RS9, and RS10. The results of the start bit noise detection is summarized in Table 26-33. PXR40 Microcontroller Reference Manual, Rev. 1 26-38 Freescale Semiconductor...
Page 967 The receiver detects the number of data bit according to the selected frame format. Table 26-34. Data Bit Sampling [RS8, RS9, RS10] Data Bit Value Noise Detected PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-39...
Page 968 4. the 0-sample of the falling edge is received at data bit N sample j, with 11 <= j <= 16. If the condition is fulfilled, the sample counter is reset 16 RCLK cycles after the 0-sample of the falling edge condition was received. The bit counter is increased by 1. PXR40 Microcontroller Reference Manual, Rev. 1 26-40 Freescale Semiconductor...
Page 969: Reception Error Reporting
If an parity error is detected, this is reported as described in Section 26.4.5.4, Reception Error Reporting. 26.4.5.4 Reception Error Reporting The receiver can detect four error types: parity errors, framing errors, noise errors, and the overrun error. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-41...
Page 970: Multiprocessor Communication
RWU bit in the Control Register 1 (eSCI_CR1) and return the receiver to the wakeup state. Frame Block Idle Character Frame Block Address Frame Receiver Wakeup Figure 26-36. Idle-Line Wakeup Format PXR40 Microcontroller Reference Manual, Rev. 1 26-42 Freescale Semiconductor...
Page 971: Lin Mode
Control Register 3 (eSCI_CR3)[M2]:= 0 • select break character length of 13 bit as required by LIN 2.0 – Control Register 2 (eSCI_CR2)[BRCL]:= 1 • select transmission stop on bit error detection PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-43...
Page 972: Lin Frame Formats
CPU write accesses to the LIN Transmit Register (eSCI_LTR). In the DMA controlled mode, the DMA controller provides the required frame configuration and frame data in response to DMA requests generated by the eSCI module. PXR40 Microcontroller Reference Manual, Rev. 1 26-44 Freescale Semiconductor...
Page 973 A block diagram which presents an overview of the DMA Controlled LIN TX Frame is shown in Figure 26-40. The content of the fields in the memory is the same as described in LIN Transmit Register (eSCI_LTR) - LIN TX frame generation. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-45...
Page 974: Lin Rx Frame Generation
LIN slave. When the module has received a complete byte field, the received data are transferred into the LIN Receive Register PXR40 Microcontroller Reference Manual, Rev. 1 26-46 Freescale Semiconductor...
Page 975 2. Enable transmitter and receiver by setting TE and RE in Control Register 1 (eSCI_CR1) to 1. 3. Setup the two DMA controller channels and provide frame header data in system memory. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-47...
Page 976: Lin Error Reporting
Fast Bit Error Detection Fast Bit Error Detection has been designed to allow flagging of LIN bit errors while they occur, rather than flagging them after a byte transmission has completed (see Figure 26-42). PXR40 Microcontroller Reference Manual, Rev. 1 26-48 Freescale Semiconductor...
Page 977 To calculate the exact position of the sample point with regard to the RX pin, the delays through the pads and the two Bus Clock cycle delay through the input synchronizer also needs to be taken into account. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-49...
Page 978: Lin Wakeup
In this case the content of the LIN Receive Register (eSCI_LRR) not changed. The data received most recently are lost. 26.4.6.6 LIN Wakeup The section describes the LIN Wakeup behavior of the eSCi module. PXR40 Microcontroller Reference Manual, Rev. 1 26-50 Freescale Semiconductor...
Page 979: Lin Protocol Engine Reset
All interrupt sources, interrupt flags, and interrupt enable bits are listed in Table 26-36. This table indicates the operational modes, where the interrupt flags can be set by the eSCI module. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-51...
Page 980: Interrupt Request Generation
— this sets the internal iCMT bit which requests the data transmission 2. wait until TDRE in Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set — this indicates the start of transmission; the iCMT bit was cleared PXR40 Microcontroller Reference Manual, Rev. 1 26-52 Freescale Semiconductor...
Page 981 — this sets the internal iCMT bit which requests the data transmission The priority scheme of the transmitter which is described in Table 26-28 ensures, that the preamble is transmitted before the data frame. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 26-53...
Page 982 Enhanced Serial Communication Interface (eSCI) PXR40 Microcontroller Reference Manual, Rev. 1 26-54 Freescale Semiconductor...
Page 983: Overview
CFIFOs to the on-chip ADCs. It also monitors the fill level of the CFIFOs and RFIFOs, and accordingly generates DMA or interrupt requests to control data movement between the FIFOs and the system memory. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 27-1...
Page 984: Analog To Digital Conversion Sub-System
CFIFOx ADC0 RQueue y ANB0 RFIFOx ADC1 STAC Bus ANB23 Interface Parallel Side Interface VDDA_AN_B VDDA_DIG_B VSSA_AN_B Decimation Filter VSSA_DIG_B VRH_B VRL_B REFBYPCB REFBYPCB1 Figure 27-1. Analog to Digital Conversion Sub-system PXR40 Microcontroller Reference Manual, Rev. 1 27-2 Freescale Semiconductor...
Page 985: Block Diagram
VDDA VSSA EQADC Parallel Side Interface (EQADC PSI) NOTE: x=0, 1, 2, 3, 4, 5 y=0, 1, 2, 3, ... On-Chip Digital Signal Processor (Decimation Filter) Figure 27-2. EQADC Block Diagram PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 27-3...
Page 986: Features
DMAC. PXR40 Microcontroller Reference Manual, Rev. 1 27-4 Freescale Semiconductor...
Page 987: Modes Of Operation
Supports 4 to 8 external 8-to-1 muxes which can expand the input channel number from 40 to 96 27.3 Modes of Operation This section describes the operation modes of the EQADC. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 27-5...
Page 988: Normal Mode
If at the time the debug mode entry request is detected, there are commands in the on-chip CBuffers that were already under execution, these commands will be completed but the generated results, if any, will not PXR40 Microcontroller Reference Manual, Rev. 1 27-6 Freescale Semiconductor...
Page 989: Stop Mode
EQADC will complete the transfer and update CFIFO status before halting future command transfers from any CFIFO. Command transfers to the internal CBuffers are considered completed when a command is written to the buffers. PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 27-7...
Page 990: External Signal Description
AN17/ANS Input Single-ended analog input / Single-ended — Analog analog input from external multiplexers AN18/ANT Input Single-ended analog input / Single-ended — Analog analog input from external multiplexers PXR40 Microcontroller Reference Manual, Rev. 1 27-8 Freescale Semiconductor...
Page 991: Detailed Signal Descriptions
Single-ended analog input/Differential analog input positive terminal. AN4 is a single-ended analog input to the two on-chip ADCs. DAN2+ is the positive terminal of the differential analog input DAN2 (DAN2+ - DAN2-). PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 27-9...
Page 992 AN19 is a single-ended analog input to the two on-chip ADCs. ANU is a single-ended analog input to one of the on-chip ADCs in external multiplexed mode. The external multiplexing capability is a device option. PXR40 Microcontroller Reference Manual, Rev. 1 27-10 Freescale Semiconductor...
Page 993: Pin Mapping To Channel Mapping
— 0, 1 0, 1 — 0, 1 0, 1 — 50% (VRH–VRL) 0, 1 0, 1 — 75% (VRH–VRL) 0, 1 0, 1 — 25% (VRH–VRL) 0, 1 0, 1 PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 27-11...
Page 994 3.3 V Internal regulator — — — 3.3 V LVD VDDSYN — — — 5.0 V LVD VDDREG — — — Standby regulator out — — — Standby source bias — — PXR40 Microcontroller Reference Manual, Rev. 1 27-12 Freescale Semiconductor...
Page 995: Memory Map/Register Definition
0x0018 EQADC_CFPR2—EQADC CFIFO Push Register 2 0x0000_0000 0x001C EQADC_CFPR3—EQADC CFIFO Push Register 3 0x0000_0000 0x0020 EQADC_CFPR4—EQADC CFIFO Push Register 4 0x0000_0000 0x0024 EQADC_CFPR5—EQADC CFIFO Push Register 5 0x0000_0000 0x0028 Reserved — PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 27-13...
Page 996 — — 0x0090 EQADC_CFTCR0—EQADC CFIFO Transfer Counter 0x0000_0000 27.6.2.8/29 Register 0 0x0094 EQADC_CFTCR1—EQADC CFIFO Transfer Counter 0x0000_0000 Register 1 0x0098 EQADC_CFTCR2—EQADC CFIFO Transfer Counter 0x0000_0000 Register 2 0x009C Reserved — — PXR40 Microcontroller Reference Manual, Rev. 1 27-14 Freescale Semiconductor...
Page 997 27.6.2.13/37 0x0250–0x0 Reserved — — 0x0300–0x0 EQADC_RF0Rw—EQADC RFIFO0 Registers (w=0, .., 3) 0x0000_0000 27.6.2.14/37 0x0310–0x0 Reserved — — 0x0340–0x0 EQADC_RF1Rw—EQADC RFIFO1 Registers (w=0, .., 3) 0x0000_0000 27.6.2.14/37 0x0350–0x0 Reserved — — PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 27-15...
Page 998: Eqadc Register Descriptions
The EQADC Module Configuration Register (EQADC_MCR) contains bits used to control how the EQADC responds to a debug mode entry request. Address: 0x0000 Access: User read/write Reset ICEA0 ICEA1 Reset Figure 27-3. EQADC Module Configuration Register (EQADC_MCR) PXR40 Microcontroller Reference Manual, Rev. 1 27-16 Freescale Semiconductor...
Page 999: Eqadc External Trigger Digital Filter Register (Eqadc_Etdfr)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset 0 Figure 27-4. EQADC External Trigger Digital Filter Register (EQADC_ETDFR) PXR40 Microcontroller Reference Manual, Rev. 1 Freescale Semiconductor 27-17...
Page 1000: Eqadc Cfifo Push Registers (Eqadc_Cfpr)
CQueues. Refer to Section 27.7.4, EQADC Command FIFOs, for more information on the CFIFOs and to Section 27.7.2.2, Message Format in EQADC, for a description on command message formats. PXR40 Microcontroller Reference Manual, Rev. 1 27-18 Freescale Semiconductor...

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Freescale Semiconductor PXR4030 Reference Manual

Chapter 1

Chapter 4

Chapter 5 Power Management Controller (PMC)

Chapter 6 Frequency Modulated Phase-Locked Loop (FMPLL)

Chapter 7 System Integration Unit (SIU)

Chapter 8 System Information Module

Chapter 9 Boot Assist Module (BAM)

Chapter 10 Interrupts and Interrupt Controller (INTC)

Chapter 11 General-Purpose Static RAM (SRAM)

Chapter 12 Flash Memory Array and Control

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