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Freescale Semiconductor KKL02Z32CAF4R Reference Manual (535 pages)

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 5 MB

Table of Contents
3
Chapter 1 About this Document

25
- Overview
  25
  - Purpose
    25
  - Audience
    25
- Conventions
  25
  - Numbering Systems
    25
  - Typographic Notation
    26
  - Special Terms
    26
Chapter 2 Introduction

27
- Overview
  27
- Kinetis L Series
  27
- KL02 Sub-Family Introduction
  30
- Module Functional Categories
  31
  - ARM Cortex-M0+ Core Modules
    32
  - System Modules
    32
  - Memories and Memory Interfaces
    33
  - Clocks
    33
  - Security and Integrity Modules
    33
  - Analog Modules
    34
  - Timer Modules
    34
  - Communication Interfaces
    35
  - Human-Machine Interfaces
    35
- Orderable Part Numbers
  35
Chapter 3 Chip Configuration

37
- Introduction
  37
- Module to Module Interconnects
  37
  - Interconnection Overview
    37
  - Analog Reference Options
    39
- Core Modules
  39
- System Modules
  46
- Clock Modules
  54
  - MCG Configuration
    54
  - OSC Configuration
    55
- Memories and Memory Interfaces
  56
- Analog
  61
  - 12-Bit SAR ADC Configuration
    61
  - CMP Configuration
    63
- Timers
  66
  - Timer/Pwm Module Configuration
    66
  - Low-Power Timer Configuration
    68
- Communication Interfaces
  70
  - SPI Configuration
    70
  - I2C Configuration
    71
  - UART Configuration
    72
- Human-Machine Interfaces (HMI)
  73
  - GPIO Configuration
    74
Chapter 4 Memory Map

77
Chapter 5 Clock Distribution

85
- Introduction
  85
- Programming Model
  85
- High-Level Device Clocking Diagram
  85
- Clock Definitions
  86
  - Device Clock Summary
    87
- Internal Clocking Requirements
  88
  - Clock Divider Values after Reset
    89
  - VLPR Mode Clocking
    89
- Clock Gating
  90
- Module Clocks
  90
  - PMC 1-Khz LPO Clock
    91
  - COP Clocking
    92
  - LPTMR Clocking
    92
  - TPM Clocking
    92
  - UART Clocking
    93
Chapter 6 Reset and Boot

95
- Introduction
  95
- Reset
  95
  - Power-On Reset (POR)
    95
  - System Reset Sources
    96
  - MCU Resets
    99
  - Reset_B Pin
    100
  - Debug Resets
    100
- Boot
  101
  - Boot Sources
    101
  - FOPT Boot Options
    101
  - Boot Sequence
    103
Chapter 7 Power Management

105
- Introduction
  105
- Clocking Modes
  105
  - Partial Stop
    105
  - Compute Operation
    106
  - Peripheral Doze
    107
  - Clock Gating
    107
- Power Modes
  108
- Entering and Exiting Power Modes
  109
- Module Operation in Low-Power Modes
  110
Chapter 8 Security

113
- Introduction
  113
- Flash Security
  113
- Security Interactions with Other Modules
  113
  - Security Interactions with Debug
    114
Chapter 9 Debug

115
- Introduction
  115
- Debug Port Pin Descriptions
  115
- SWD Status and Control Registers
  116
  - MDM-AP Control Register
    117
  - MDM-AP Status Register
    118
- Debug Resets
  120
- Micro Trace Buffer (MTB)
  120
- Debug in Low-Power Modes
  121
- Debug and Security
  122
Chapter 10 Signal Multiplexing and Signal Descriptions

123
- Introduction
  123
- Signal Multiplexing Integration
  123
  - Port Control and Interrupt Module Features
    124
  - Clock Gating
    125
  - Signal Multiplexing Constraints
    125
- Pinout
  125
  - KL02 Signal Multiplexing and Pin Assignments
    125
  - KL02 Pinouts
    126
- Module Signal Description Tables
  127
  - Core Modules
    127
  - System Modules
    127
  - Clock Modules
    128
  - Memories and Memory Interfaces
    128
  - Analog
    128
  - Timer Modules
    129
  - Communication Interfaces
    129
  - Human-Machine Interfaces (HMI)
    130
Chapter 11 Port Control and Interrupts (PORT)

131
- Introduction
  131
- Overview
  131
  - Features
    131
  - Modes of Operation
    132
- External Signal Description
  132
- Detailed Signal Description
  133
- Memory Map and Register Definition
  133
  - Pin Control Register N (Portx_Pcrn)
    136
Chapter 13 System Mode Controller (SMC)

163
- Introduction
  163
- Modes of Operation
  163
- Memory Map and Register Descriptions
  165
- Power Mode Protection Register (SMC_PMPROT)
  165
- Power Mode Control Register (SMC_PMCTRL)
  167
- Stop Control Register (SMC_STOPCTRL)
  168
- Power Mode Status Register (SMC_PMSTAT)
  169
- Functional Description
  170
- Power Mode Transitions
  170
- Power Mode Entry/Exit Sequencing
  173
- Run Modes
  175
- Wait Modes
  176
- Stop Modes
  177
- Debug in Low Power Modes
  179
Chapter 14 Power Management Controller (PMC)

181
- Introduction
  181
- Features
  181
- Low-Voltage Detect (LVD) System
  181
- LVD Reset Operation
  182
- LVD Interrupt Operation
  182
- Low-Voltage Warning (LVW) Interrupt Operation
  182
- I/O Retention
  183
- Memory Map and Register Descriptions
  183
- Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)
  184
- Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)
  185
- Regulator Status and Control Register (PMC_REGSC)
  186
Chapter 15 Reset Control Module (RCM)

189
Chapter 16 Bit Manipulation Engine (BME)

195
- Introduction
  195
- Overview
  196
- Features
  196
- Modes of Operation
  197
- External Signal Description
  197
- Memory Map and Register Definition
  198
- Functional Description
  198
- BME Decorated Stores
  198
- BME Decorated Loads
  205
- Additional Details on Decorated Addresses and GPIO Accesses
  211
- Application Information
  212
Chapter 17 Miscellaneous Control Module (MCM)

215
Chapter 18 Micro Trace Buffer (MTB)

223
- Introduction
  223
- Overview
  223
- Features
  226
- Modes of Operation
  227
- External Signal Description
  227
- Memory Map and Register Definition
  228
- MTB_RAM Memory Map
  228
- MTB_DWT Memory Map
  240
- System ROM Memory Map
  252
Chapter 19 Crossbar Switch Lite (AXBS-Lite)

257
- Introduction
  257
- Features
  257
- Memory Map / Register Definition
  257
- Functional Description
  258
- General Operation
  258
- Arbitration
  259
- Initialization/Application Information
  260
Chapter 20 Peripheral Bridge (AIPS-Lite)

261
- Introduction
  261
- Features
  261
- General Operation
  261
- Functional Description
  262
- Access Support
  262
Chapter 21 Multipurpose Clock Generator (MCG)

263
- Introduction
  263
- Features
  263
- Modes of Operation
  266
- External Signal Description
  266
- Memory Map/Register Definition
  266
- MCG Control 1 Register (MCG_C1)
  266
- MCG Control 2 Register (MCG_C2)
  267
- MCG Control 3 Register (MCG_C3)
  269
- MCG Control 4 Register (MCG_C4)
  269
- MCG Control 6 Register (MCG_C6)
  271
- MCG Status Register (MCG_S)
  271
- MCG Status and Control Register (MCG_SC)
  272
- MCG Auto Trim Compare Value High Register (MCG_ATCVH)
  274
- MCG Auto Trim Compare Value Low Register (MCG_ATCVL)
  274
- Functional Description
  274
- MCG Mode State Diagram
  274
- Low Power Bit Usage
  278
- MCG Internal Reference Clocks
  278
- External Reference Clock
  279
- MCG Fixed Frequency Clock
  279
- MCG Auto TRIM (ATM)
  279
- Initialization / Application Information
  281
- MCG Module Initialization Sequence
  281
- Using a 32.768 Khz Reference
  283
- MCG Mode Switching
  284
Chapter 22 Oscillator (OSC)

287
- Introduction
  287
- Features and Modes
  287
- Block Diagram
  288
- OSC Signal Descriptions
  288
- External Crystal / Resonator Connections
  289
- External Clock Connections
  290
- Memory Map/Register Definitions
  291
- OSC Memory Map/Register Definition
  291
- Functional Description
  292
- OSC Module States
  292
- OSC Module Modes
  294
- Counter
  295
- Reference Clock Pin Requirements
  295
- Reset
  296
- Low Power Modes Operation
  296
- Interrupts
  296
Chapter 23 Flash Memory Controller (FMC)

297
- Introduction
  297
- Overview
  297
- Features
  297
- Modes of Operation
  298
- External Signal Description
  298
- Memory Map and Register Descriptions
  298
- Functional Description
  298
Chapter 24 Flash Memory Module (FTFA)

301
- Introduction
  301
- Features
  302
- Block Diagram
  302
- Glossary
  303
- External Signal Description
  304
- Memory Map and Registers
  304
- Flash Configuration Field Description
  304
- Program Flash IFR Map
  305
- Register Descriptions
  306
- Functional Description
  315
- Flash Protection
  315
- Interrupts
  316
- Flash Operation in Low-Power Modes
  316
- Functional Modes of Operation
  317
- Flash Reads and Ignored Writes
  317
- Read While Write (RWW)
  317
- Flash Program and Erase
  317
- Flash Command Operations
  317
- Margin Read Commands
  322
- Flash Command Description
  323
- Security
  336
- Reset Sequence
  338
Chapter 25 Analog-To-Digital Converter (ADC)

339
- Introduction
  339
- Features
  339
- Block Diagram
  340
- ADC Signal Descriptions
  341
- Analog Power (VDDA)
  342
- Analog Ground (VSSA)
  342
- Analog Channel Inputs (Adx)
  342
- Memory Map and Register Definitions
  342
- ADC Status and Control Registers 1 (Adcx_Sc1N)
  343
- ADC Configuration Register 1 (Adcx_Cfg1)
  347
- ADC Configuration Register 2 (Adcx_Cfg2)
  348
- ADC Data Result Register (Adcx_Rn)
  349
- Compare Value Registers (Adcx_Cvn)
  350
- Status and Control Register 2 (Adcx_Sc2)
  351
- Status and Control Register 3 (Adcx_Sc3)
  353
- ADC Offset Correction Register (Adcx_Ofs)
  355
- ADC Plus-Side Gain Register (Adcx_Pg)
  355
- ADC Plus-Side General Calibration Value Register (Adcx_Clpd)
  356
- ADC Plus-Side General Calibration Value Register (Adcx_Clps)
  356
- ADC Plus-Side General Calibration Value Register (Adcx_Clp4)
  357
- ADC Plus-Side General Calibration Value Register (Adcx_Clp3)
  357
- ADC Plus-Side General Calibration Value Register (Adcx_Clp2)
  358
- ADC Plus-Side General Calibration Value Register (Adcx_Clp1)
  358
- ADC Plus-Side General Calibration Value Register (Adcx_Clp0)
  359
- Functional Description
  359
- Clock Select and Divide Control
  360
- Voltage Reference Selection
  360
- Hardware Trigger and Channel Selects
  361
- Conversion Control
  362
- Automatic Compare Function
  368
- Calibration Function
  370
- User-Defined Offset Function
  371
- Temperature Sensor
  372
- MCU Wait Mode Operation
  373
- MCU Normal Stop Mode Operation
  373
- MCU Low-Power Stop Mode Operation
  374
- Initialization Information
  375
- ADC Module Initialization Example
  375
- Application Information
  377
- External Pins and Routing
  377
- Sources of Error
  379
Chapter 26 Comparator (CMP)

383
- Introduction
  383
- CMP Features
  383
- 6-Bit DAC Key Features
  384
- ANMUX Key Features
  384
- CMP, DAC and ANMUX Diagram
  385
- CMP Block Diagram
  386
- Memory Map/Register Definitions
  387
- CMP Control Register 0 (Cmpx_Cr0)
  387
- CMP Control Register 1 (Cmpx_Cr1)
  388
- CMP Filter Period Register (Cmpx_Fpr)
  390
- CMP Status and Control Register (Cmpx_Scr)
  390
- DAC Control Register (Cmpx_Daccr)
  391
- MUX Control Register (Cmpx_Muxcr)
  392
- Functional Description
  393
- CMP Functional Modes
  393
- Power Modes
  402
- Startup and Operation
  403
- Low-Pass Filter
  403
- CMP Interrupts
  406
- Digital-To-Analog Converter
  406
- DAC Functional Description
  407
- Voltage Reference Source Select
  407
- DAC Resets
  407
- DAC Clocks
  407
- DAC Interrupts
  408
- CMP Trigger Mode
  408
Chapter 27 Timer/Pwm Module (TPM)

409
- Introduction
  409
- TPM Philosophy
  409
- Features
  409
- Modes of Operation
  410
- Block Diagram
  410
- TPM Signal Descriptions
  411
- TPM_EXTCLK - TPM External Clock
  411
- Tpm_Chn - TPM Channel (N) I/O Pin
  412
- Memory Map and Register Definition
  412
- Status and Control (Tpmx_Sc)
  413
- Counter (Tpmx_Cnt)
  414
- Modulo (Tpmx_Mod)
  415
- Channel (N) Status and Control (Tpmx_Cnsc)
  416
- Channel (N) Value (Tpmx_Cnv)
  417
- Capture and Compare Status (Tpmx_Status)
  418
- Configuration (Tpmx_Conf)
  420
- Functional Description
  421
- Clock Domains
  422
- Prescaler
  422
- Counter
  423
- Input Capture Mode
  425
- Output Compare Mode
  426
- Edge-Aligned PWM (EPWM) Mode
  427
- Center-Aligned PWM (CPWM) Mode
  429
- Registers Updated from Write Buffers
  431
- Reset Overview
  432
- TPM Interrupts
  432
Chapter 28 Low-Power Timer (LPTMR)

433
- Introduction
  433
- Features
  433
- Modes of Operation
  433
- LPTMR Signal Descriptions
  434
- Detailed Signal Descriptions
  434
- Memory Map and Register Definition
  434
- Low Power Timer Control Status Register (Lptmrx_Csr)
  435
- Low Power Timer Prescale Register (Lptmrx_Psr)
  436
- Low Power Timer Compare Register (Lptmrx_Cmr)
  438
- Low Power Timer Counter Register (Lptmrx_Cnr)
  438
- Functional Description
  439
- LPTMR Power and Reset
  439
- LPTMR Clocking
  439
- LPTMR Prescaler/Glitch Filter
  439
- LPTMR Compare
  441
- LPTMR Counter
  441

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Freescale Semiconductor KKL02Z32CAF4R Manuals

Freescale Semiconductor KKL02Z32CAF4R Reference Manual (535 pages)

Table of Contents

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Chip Configuration

Chapter 4 Memory Map

Chapter 5 Clock Distribution

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10 Signal Multiplexing and Signal Descriptions

Chapter 11 Port Control and Interrupts (PORT)

Chapter 13 System Mode Controller (SMC)

Chapter 14 Power Management Controller (PMC)

Chapter 15 Reset Control Module (RCM)

Chapter 16 Bit Manipulation Engine (BME)

Chapter 17 Miscellaneous Control Module (MCM)

Chapter 18 Micro Trace Buffer (MTB)

Chapter 19 Crossbar Switch Lite (AXBS-Lite)

Chapter 20 Peripheral Bridge (AIPS-Lite)

Chapter 21 Multipurpose Clock Generator (MCG)

Chapter 22 Oscillator (OSC)

Chapter 23 Flash Memory Controller (FMC)

Chapter 24 Flash Memory Module (FTFA)

Chapter 25 Analog-To-Digital Converter (ADC)

Chapter 26 Comparator (CMP)

Chapter 27 Timer/Pwm Module (TPM)

Chapter 28 Low-Power Timer (LPTMR)

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