Interr�Pt Operation - Holtek HT46R003B Manual

INTC1 Register
Bit 7
Name —
R/W —
POR —
Bit 7~5 Unimplemented, read as "0"
TBF: time base event interrupt request flag
Bit 4
0: No request
1: Interrupt request
Bit 3~1 Unimplemented, read as "0"
TBE: time base event interrupt enable
Bit 0
0: Disable
1: Enable
Interrupt Operation
A Timer/Event Counter overflow, a completion of A/D conversion or an active edge on the external
interrupt pin will all generate an interrupt request by setting their corresponding request flag, if
their appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores
the address of the next instruction to be executed, will be transferred onto the stack. The Program
Counter will then be loaded with a new address which will be the value of the corresponding
interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector.
The instruction at this vector will usually be a JMP statement which will jump to another section
of program which is known as the interrupt service routine. Here is located the code to control the
appropriate interrupt. The interrupt service routine must be terminated with a RETI instruction,
which retrieves the original Program Counter address from the stack and allows the microcontroller
to continue with normal execution at the point where the interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
following diagram with their order of priority.
Interrupt
Name
INT Pin
Timer
A/D
Time Base
Rev. 1.00
Cost-Effective A/D 8-bit OTP MCU
6 5 4
— — TBF
— — R/W
— — 0
EMI auto disabled in ISR
Request Enable Master
Flags Bits Enable
INTF INTE EMI
TF TE EMI
ADF ADE EMI
TBF TBE EMI
Interrupt Scheme
5�
HT46R003B
3 2 1
— — —
— — —
— — —
Legend
xxF Request Flag - auto reset in ISR
xxE Enable Bit
Priority
Vector
High
04H
08H
0CH
10H
Low
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0
TBE
R/W
0