Port A Wake-�P; I/O Port Control Registers - Holtek HT46R003B Manual

HT46R003B
Cost-Effective A/D 8-bit OTP MCU
PBPU Register
Bit
Name —
R/W —
POR —
Bit 7~6 Unimplemented, read as "0"
PBPU5~PBPU0: Port B bit 5~bit 0 pull-high control
Bit 5~0
0: Disable
1: Enable
Port A Wake-up
If the HALT instruction is executed, the device will enter the Sleep Mode, where the system clock will
stop resulting in power being conserved, a feature that is important for battery and other low-power
applications. Various methods exist to wake-up the microcontroller, one of which is to change the
logic condition on one of the PA0~PA7 pins from high to low. After a HALT instruction forces the
microcontroller into entering the Sleep Mode, the processor will remain in a low-power state until
the logic condition of the selected wake-up pin on Port A changes from high to low. This function
is especially suitable for applications that can be woken up via external switches. Note that pins
PA0~PA7 can be selected individually to have this wake-up feature using an internal register known
as PAWU, located in the Data Memory.
PAWU Register
Bit 7
Name PAWU7
R/W R/W
POR
PAWU7~PAWU0: Port A bit 7~bit 0 wake-up control
Bit 7~0
0: Disable
1: Enable

I/O Port Control Registers

Each port has its own control register known as PAC, PBC, which control the input/output
configuration. With this control register, each I/O pin with or without pull-high resistors can be
reconfigured dynamically under software control. For the I/O pin to function as an input, the
corresponding bit of the control register must be written as a "1". This will then allow the logic
state of the input pin to be directly read by instructions. When the corresponding bit of the control
register is written as a "0", the I/O pin will be set as a CMOS output. If the pin is currently set as an
output, instructions can still be used to read the output register. However, it should be noted that the
program will in fact only read the status of the output data latch and not the actual logic status of the
output pin.
PAC Register
Bit 7
Name PAC7
R/W R/W
POR 1
PAC7~PAC0: Port A bit 7 ~ bit 0 Input/Output control
Bit 7~0
0: Output
1: Input
Rev. 1.00
7 6 5
— PBPU5 PBPU�
— R/W
— 0
6 5
PAWU6 PAWU5 PAWU�
R/W R/W
0 0 0
6 5
PAC6 PAC5
R/W R/W
1 1
31
4 3 2
PBPU3 PBPU�
R/W R/W R/W
0 0 0
4 3 2
PAWU3 PAWU�
R/W R/W R/W
0 0 0
4 3 2
PAC� PAC3 PAC�
R/W R/W R/W
1 1 1
1 0
PBPU1 PBPU0
R/W R/W
0 0
1 0
PAWU1 PAWU0
R/W R/W
0 0
1 0
PAC1 PAC0
R/W R/W
1 1
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