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3-9 10 MHz REFERENCE OSCILLATOR (81772): The main frequency standard for
the RX340 is a 10-MHz, high-stability TCVCXO that can be locked to an external
reference of 1, 2, 5, or 10 MHz. Differential amplifier Q1, Q2 presents a high impedance
to board connector 63 and External Reference jack J2. A sample of Q2's output is
rectified by level-detector D1 and compared to a threshold voltage by U3a. When the
external reference amplitude exceeds the threshold set by U3a, transistors Q3-Q5 turn
OFF, allowing the gate of switch Q6 to pull high and switch the FET ON. This connects
the filtered output of PLL U1 to the TCVCXO tuning pin (pin-1) and completes the loop
to lock the TCVCXO to 10 MHz. When no external reference is applied, transistors Q3-
Q5 conduct, holding Q6's gate low. In this condition, the TCVCXO range is set by
trimpot R32, and the open-loop TCVCXO becomes the frequency standard for the
receiver.
3-10 DSP/CPU (81807): Refer to Figure (10-2). The DSP/CPU board contains two
separate processor systems; the MAIN CPU (U1) which controls the RX-340 interface,
and the DSP CPU (U15) which performs signal-processing functions. The two systems'
busses integrate through an I/O expansion IC (U11). Communication between the MAIN
CPU and the DSP CPU is handled by a combination of hardware and software, providing
bi-directional data capability.
The main CPU system consists of CPU (U1), CPLD (U4), ROM (U12) and battery
backed RAM (U3) (See Figures 10-37, 38). Latches U5 and U6 buffer rear panel switch
settings, while a portion of CPLD U4 is used for address control. Serial/parallel
converter U28 adds additional output capability to the system. RS-232 interface
controller chip (U2) handles buffering and level translation for the Multi-drop network.
This is a special RS-232 IC that allows its output to be completely turned OFF when not
active. It is this feature of U2 that permits multiple connects to a common RS-232 bus.
Audio outputs are monitored by U1 via an internal A/D converter.
U17, U23 and U24 process the DSP digital output. A programmable-logic device, U17,
converts the DSP serial output data to a dual-byte, parallel output and creates the
HIBYTE/LOWBYTE, STROBE, IF/AF and USB/LSB control signals. Latches U23 and
U24 provide output buffering for the data and control signals. In addition, U23 and U24
add tri-state capability to the interface which can be selected via software command.
The DSP system core consists of the DSP Processor (U15), ROM (U30), and AGC DAC
(U18). The DSP system is connected to the I/O converter board via connectors 4, 5, 18
and 64. Serial data travels from the converter board to the DSP CPU at a 66-2/3 kHz
sample rate. After signal processing, serial data travels to the converter board at twice
the input rate, or 133-1/3 kHz. The DSP output data is multiplexed to provide audio and
IF data to the converter board which de-multiplexes the data and directs it to the proper
output.
The RX-340 provides programmable AGC which is implemented as a combination of
hardware and DSP software. The DSP system provides an analog AGC control voltage
output on connector J17 which is delivered to the second mixer board. Circuitry on the
3-9
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