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3-4 FIRST MIXER (81823): Refer to figure (10-13). Signals from the preselector
board are routed through a 30-MHz low-pass filter (L7-L10) and sent to the RF-input port
of high-level balanced mixer D1-D4 (T3). The 1st-LO signal is amplified by Q1 and
routed through a low-bandpass filter (L5, L6) for application to the mixer's LO port (T2).
The resultant mixer products appear at output port T4. Here, signals are divided, with
one branch routed via balun T5 to the rear-panel 1st-Mixer Output (J9). The other branch
is applied to a high-level push-pull parallel FET amplifier stage Q2-Q7. This stage
boosts signals prior to filtering by FL1- FL2. FL1-FL2 are 45.455-MHz crystal roofing
filters cascaded to provide a 4-pole response for rejecting the unwanted mixer image plus
other spurious products. Post-filter amplifier Q8 boosts the level of the selected 45.455-
MHz IF product prior to application to the 2nd mixer.
RD
nd
rd
3-5 SECOND MIXER / 3
LO (81817): The 2
mixer / 3
LO board down-converts
the 45.455 MHz 1st IF to the 455 kHz 2nd IF, and 16-2/3 kHz 3rd IF, respectively. It
also provides outputs to the following connector locations: 2nd Mixer output (J10),
Signal Monitor output (J3), A/D converter (51), AGC DET (16), AGC control (7A) and
LO3 (52). Inputs are: 1st IF (5A), LO2 (55), 10-MHz reference (57), PLL data (12),
AGC DAC (17), power ±5V (20) and +12V (21).
Refer to schematic Figure (10-18). The 1st-IF signal (45 .455 MHz) is applied to high-
level diode-ring mixer D3-D6 at input-port T4. The 2nd-LO is amplified by Q7, filtered
at L3-L5, and applied to the mixer's LO port T5. The resulting products are buffered by
a parallel FET common-gate array Q10-Q13. A smaller sample of the mixer's output is
buffered by Q8-Q9 and routed to 2nd mixer out, connector J10. The desired 455-kHz
2nd-IF product is selected by ceramic band pass filter FL1 and fed to controlled-gain IF-
amplifier U6. The output of U6 is post-filtered by FL2 and split three ways. One leg is
applied to AGC detector Q14-Q15, which pulls the voltage on AGC integrating
capacitors C71-C73 low at a rate of 31.25 mV per dB when the output signal exceeds a
threshold set by AGC-ADJ pot R97. A second leg is applied to op-amp U7a, which
buffers the 455-kHz IF output and applies it to the Signal Monitor jack (J3). The
remaining leg is applied to 3rd-mixer U4, a Gilbert-Cell DBM. A 471-2/3 kHz 3rd-LO
signal is also applied to mixer U4 to yield a 3rd-IF output of 16-2/3 kHz. This product
passes through anti-aliasing, low pass filter U5 to the 3rd-IF output connector 59. R81
nulls DC-offset from the 3rd-IF output line.
AGC-detector voltage is buffered by op-amp U7b and routed to AGC-DET connector 16.
Op-amp U8b provides a means for setting the IF gain externally via AGC-DAC
connector 17. The D/A converter connected to AGC-DAC pulls the AGC detector
voltage low, overriding AGC detector output and reducing IF gain at the rate of 32
dB/Volt. A high-level output from Q16 to AGC control connector 74 (pin-D) indicates
when the DAC is overriding the AGC detector. A high-level output from U8a to 74 (pin-
A) indicates the AGC detector is overriding the DAC. The combination of U8a and Q16
can be thought of as a 2-bit ADC with 1-dB hysteresis. PLL U3, charge pump Q1-Q4,
VCO Q5, and dividers U1-U2 develop the third Local Oscillator frequency of 471-2/3
kHz. This signal is applied to both 3rd-Mixer U4 and the 3rd-LO output connector 52.
3-6
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