Quectel BG95 Series Hardware Design page 46

Table 13: Pin Definition of Debug UART Interface
Pin Name Pin No.
DBG_RXD 22
DBG_TXD 23
Table 14: Pin Definition of GNSS UART Interface
Pin Name
GNSS_UART_TXD
GNSS_UART_RXD
The logic levels of UART interfaces are described in the following table.
Table 15: Logic Levels of Digital I/O
Parameter
V
IL
V
IH
V
OL
V
OH
The module provides 1.8V UART interface. A level translator should be used if customers' application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments
is recommended. The following figure shows a reference design of the Main UART interface:
BG95_Hardware_Design
I/O Description
DI Receive data
DO Transmit data
Pin No. I/O
27 DO
28 DI
Min.
-0.3
1.2
0
1.35
Description
Transmit data
Receive data
Max.
0.6
2.0
0.45
1.8
LPWA Module Series
BG95 Hardware Design
Comment
1.8V power domain
1.8V power domain
Comment
1.8V power domain
1.8V power domain
Unit
V
V
V
V
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