Table of Contents
Advertisement
19.2 Operation List
Mnemonic
MOV
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL+byte]
[HL+byte], A
XCH
A, X
A, r
A, saddr
A, sfr
A, [DE]
A, [HL]
A, [HL+byte]
Notes 1. Except r = A.
2. Except r = A, X.
Remark
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
CHAPTER 19 INSTRUCTION SET
Operands
Byte
3
3
3
Note 1
2
Note 1
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
Note 2
2
2
2
1
1
2
User's Manual U15075EJ1V0UM00
Clock
r ← byte
6
(saddr) ← byte
6
sfr ← byte
6
A ← r
4
r ← A
4
A ← (saddr)
4
(saddr) ← A
4
A ← sfr
4
sfr ← A
4
A ← (addr16)
8
(addr16) ← A
8
PSW ← byte
6
A ← PSW
4
PSW ← A
4
A ← (DE)
6
(DE) ← A
6
A ← (HL)
6
(HL) ← A
6
A ← (HL + byte)
6
(HL + byte) ← A
6
A ↔ X
4
A ↔ r
6
A ↔ (saddr)
6
A ↔ sfr
6
A ↔ (DE)
8
A ↔ (HL)
8
A ↔ (HL + byte)
8
) selected by the processor clock control
CPU
Operation
Flag
Z AC CY
x
x
x
x
x
x
301
Advertisement
Table of Contents
