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CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES)
11.4 10-Bit A/D Converter Operation
11.4.1 Basic operation of 10-bit A/D converter
<1> Select a channel for A/D conversion, using analog input channel specification register 0 (ADS0).
<2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit.
<3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the
input analog voltage until A/D conversion is completed.
<4> Bit 9 of the successive approximation register (SAR) is set. The series resistor string tap voltage at the
tap selector is set to half of AV
<5> The series resistor string tap voltage is compared with the analog input voltage using the voltage
comparator. If the analog input voltage is higher than half of AV
lower than half of AV
<6> Bit 8 of SAR is set automatically, and comparison shifts to the next stage. The next tap voltage of the
series resistor string is selected according to bit 9, which reflects the previous comparison result, as
follows:
• Bit 9 = 1: Three quarters of AV
• Bit 9 = 0: One quarter of AV
The tap voltage is compared with the analog input voltage. Bit 8 is set or reset according to the result of
comparison.
• Analog input voltage ≥ tap voltage: Bit 8 = 1
• Analog input voltage < tap voltage: Bit 8 = 0
<7> Comparison is repeated until bit 0 of SAR is reached.
<8> When comparison is completed for all of the 10 bits, a significant digital result is left in SAR. This value
is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to
generate an A/D conversion end interrupt request (INTAD0).
Cautions 1. The first A/D conversion value immediately after A/D conversion has been started may be
undefined.
2. In standby mode, A/D converter operation is stopped.
202
.
DD
, the MSB is reset.
DD
DD
DD
User's Manual U15075EJ1V0UM00
, the MSB of SAR is left set. If it is
DD
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