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Mnemonic
MOVW
rp, #word
AX, saddrp
saddrp, AX
AX, rp
rp, AX
AX, rp
XCHW
ADD
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
ADDC
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
SUB
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
Note Only when rp = BC, DE, or HL.
Remark
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
302
CHAPTER 19 INSTRUCTION SET
Operands
Byte
3
2
2
Note
1
Note
1
Note
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
User's Manual U15075EJ1V0UM00
Clock
rp ← word
6
AX ← (saddrp)
6
(saddrp) ← AX
8
AX ← rp
4
rp ← AX
4
AX ↔ rp
8
A, CY ← A + byte
4
(saddr), CY ← (saddr) + byte
6
A, CY ← A + r
4
A, CY ← A + (saddr)
4
A, CY ← A + (addr16)
8
A, CY ← A + (HL)
6
A, CY ← A + (HL + byte)
6
A, CY ← A + byte + CY
4
(saddr), CY ← (saddr) + byte + CY
6
A, CY ← A + r + CY
4
A, CY ← A + (saddr) + CY
4
A, CY ← A + (addr16) + CY
8
A, CY ← A + (HL) + CY
6
A, CY ← A + (HL + byte) + CY
6
A, CY ← A − byte
4
(saddr), CY ← (saddr) − byte
6
A, CY ← A − r
4
A, CY ← A − (saddr)
4
A, CY ← A − (addr16)
8
A, CY ← A − (HL)
6
A, CY ← A − (HL + byte)
6
) selected by the processor clock control
CPU
Operation
Flag
Z AC CY
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
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