Configuration Options; S/Pdif Or Psia In To Analog Out; Figure 2.S/Pdif Or Psia In To Analog Out - Cirrus Logic CDB42L55 Manual

3 CONFIGURATION OPTIONS

This section highlights two common configurations for the CDB42L55. It provides a basic understanding of how the
various components on the board work together.
3.1

S/PDIF or PSIA In to Analog Out

The CS42L55 analog back-end performance can be tested by selecting the "SPDIF In to Analog Out --
Analog In to S/PDIF Out" or "PSIA In to Analog Out -- Analog In to PSIA Out" quick setup file provided
with the software package. Note: The Control Port Compensation script for the associated VA supply
must also be selected. The script configures the digital clock and data signal routing on the board as shown
in Figure 2. The quick setup scripts provided in the software assume that a 24.000 MHz on-board oscillator
is populated in Y1.
A S/PDIF input must be provided as the S/PDIF Tx (CS8406) uses the RMCK signal from the S/PDIF Rx
(CS8416) for synchronization in this configuration.
PSIA Tx (J78)
TX.SCLK
Out
TX.LRCK
Out
TX.SDOUT
S/PDIF Rx
(CS8416)
RX.LRCK
RX.SCLK
S/PDIF
RX.SDOUT
IN (Master)
8
FPGA
Tx SRC
(CS8421)
(Slave)
Figure 2. S/PDIF or PSIA In to Analog Out
An on-board PLL generates all supported sample and
bit clock rates from an on-board 24 MHz oscillator.
PLL
MCLK
CS42L55
LINEOUTB
SCLK
LINEOUTA
LRCK
HPOUTB
J4
DAC.SDIN 32
32
J12
HPOUTA
(Slave)
CDB42L55
24 MHz
(on-board osc.)
B
A
Line
Channel
J3 B
16
16
J2 A
HP
Channel
HP
J21
Connection
DS773DB1