Imx21 Bus Cycle Setting Example - Epson S1R72V17 Connection Manual

5. Connection Example with FreeScale iMX21
5.2

iMX21 Bus Cycle Setting Example

• iMX21 clock settings
The iMX21 clock settings are set as shown below in this connection example.
System clock: 264 MHz
CPU-IF bus clock (HCLK): 88 MHz (system clock 3 divisions)
• Bus cycle settings
CS1U register (0xDF001008 address)
31 30
SP WP
15 14
CNC
CS1L register (0xDF00100C address)
31 30
15 14
Setting descriptions
Register
RWA
SYNC
RWN
WSC
WWS
OEA
OEN
WEA
WEN
CSA
EBC
DSZ
CSN
CSEN
16
29 28 27 26
DCT RWA
13 12 11 10
WSC
29 28 27 26
OEA OEN
13 12 11 10
CSA EBC
Setting Description
4'b0100 RW output assert timing (2HCLK)
1'b0
Synchronous transfer mode (disabled)
4'b0010 RW output negate timing (1HCLK)
6'b000111 Access cycle (8HCLK)
3'b000 Wait cycle for write (0HCLK)
4'b0100 OE output assert timing (2HCLK)
4'b0010 OE output negate timing (1HCLK)
4'b0000 EBx output assert timing (0HCLK)
4'b0000 EBx output negate timing (0HCLK)
4'b0000 CS1 output assert timing (0HCLK)
1'b1 EB3, 2 output mode for read (disabled)
3'b101
Data bus size (using 16 bits [15:0])
4'b0000 CS1 output assert timing (0HCLK)
1'b1 CS1 enable (enabled)
Fig. 5-2 Bus cycle setting registers
Setting: 0x0402_0700
25 24 23 22 21
PSZ PME SYNC
9 8 7 6 5
EW WWS
Setting: 0x4200_0D01
25 24 23 22 21
WEA
9 8 7 6 5
DSZ CSN
EPSON
20 19 18 17 16
RWN
4 3 2 1 0
EDC
20 19 18 17 16
WEN
4 3 2 1 0
PSR CRE WRAPCSEN
S1R72V17 CPU Connection Guide
(Rev. 1.0)