Epson S1R72V17 Connection Manual page 12

3. Endian Settings for 16-bit Bus Width Connection
2) Access to Byte register
The S1R72V17 connects the D[7:0] bus to the even-number address register and the D[15:8] bus
to the odd-number address register when the CPU_Endian bit is set to "1."
The example below illustrates the writing and reading of F1h to/from the Byte register
even-number address register and of F2h to/from the Byte register odd-number address register.
Writing:
Reading:
CPU
S1R72V17
8
The data (F1h) in the CPU memory even-number address is saved to the
S1R72V17 even-number address register.
The S1R72V17 even-number address register data (F1h) is saved to the
even-number address in CPU memory.
Data
Higher byte [15:8]
F2h
D[15:8]
D[15:8]
F2h
Odd-number address
register
Fig. 3-5 Access to Byte registers (little-endian CPU)
・・・・
・・・・
F1h Even-number address
F2h Odd-number address
・・・・
・・・・
Lower byte [7:0]
F1h
D[7:0]
D[15:0] bus connected unchanged
D[7:0]
F1h
Even-number address
register
EPSON
Data in CPU memory
CPU register
CPU data bus
V17 data bus
V17 Byte register
S1R72V17 CPU Connection Guide
(Rev. 1.0)