Epson S1R72V17 Connection Manual page 10

3. Endian Settings for 16-bit Bus Width Connection
3) Access to FIFO register
The S1R72V17 connects the D[15:8] bus to the even-number address register and the D[7:0] bus
to the odd-number address register when the CPU_Endian bit is set to "0."
The example below illustrates transmission from the USB bus in the sequence C1h/C2h and
receiving in the sequence C1h/C2h.
Writing:
Reading:
CPU
S1R72V17
6
The data (C1h) in the CPU memory even-number address is sent from the USB
bus as the first data.
The first data received from the USB bus (C1h) is saved to the even-number
address in CPU memory.
Data
・・・・
・・・・
C1h
C2h
・・・・
・・・・
Higher byte [15:8]
C1h
D[15:8]
D[15:8]
C2h
Odd-number address
register
Data[15:8]
・・・・
・・・・
(2) C2h
(4) ・・・・
・・・・
・・・・
Fig. 3-3 Access to FIFO registers (big-endian CPU)
Even-number address
Odd-number address
Lower byte [7:0]
C2h
D[7:0]
D[15:0] bus connected unchanged
D[7:0]
C1h
Even-number address
register
Data[7:0]
・・・・
・・・・
(1) C1h Sent via USB bus in order (1), (2).
(3) ・・・・
・・・・
・・・・
EPSON
Data in CPU memory
CPU register
CPU data bus
V17 data bus
V17 Byte register
V17 FIFO data
S1R72V17 CPU Connection Guide
(Rev. 1.0)