Silicon Laboratories Si4010 Software Programming Manual page 94

AN370
where T_clk_sys_entry is the period of the system clock with which the function was
entered and T_clk_sys_fast is the clock period of the system clock with SYSCLK_DIV =
0 setting. Nominally, it is 1/24 MHz = 41.667 ns.
The longest delay this function can produce is 35 + 255 x 10 = 2585 cycles, resulting in
107 µs delay. The delay resolution is 10 cycles, corresponding to 0.417 µs.
The function does not disable any interrupts. It is fully interruptible. If the user does not
desire this function to be interrupted he has to disable the interrupts prior to calling this
function.
Inputs:
biIntervalCount: (BYTE) Determines the number of system clock cycles spent
inside of the function as shown in the expression above.
Outputs:
None
94 Rev. 1.0