8051 Internal Memory; Memory Map - Silicon Laboratories Si4010 Software Programming Manual

3.1. 8051 Internal Memory

Figure 1 shows the Si4010 memory which is internal to the 8051 MCU.

3.2. Memory Map

After the chip boots, the memory on the Si4010 is mapped as shown in Figure 2. The 4.5 kB RAM section is
accessible both as CODE and XDATA (MOVC and MOVX instructions). The XREG region is accessible only as
XDATA (MOVX). The ROM is not accessible as data, but the code residing in ROM can be executed. The NVM is
virtually mapped into this region, but is not directly accessible by CPU. The NVM API functions must be used to
access the NVM.
Figure 2. Si4010 Unified CODE/XDATA Memory Organization
Internal Memory
Both direct and indirect addressing
0x00
DATA
0x7F
0x80
SFR
(DATA)
0xFF
Direct addressing only
MOV A, addr
Figure 1. CPU Internal Memory Organization
0x0000
0x11FF
0x4000
0x40FF
0x8000
0xAFFF
0xE000
0xFFFF
Virtual mapping, not directly
accessible by CPU
Rev. 1.0
0x80
IDATA
0xFF
Indirect addressing only
by @Ri pointers
MOV A, @Ri
CODE/
XDATA
RAM 4.5K
XREG
ROM 12K
NVM 8K
AN370
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