Interrupt And System Impact Of Some Functions; Interrupt Priorities - Silicon Laboratories Si4010 Software Programming Manual

AN370

6. Interrupt and System Impact of Some Functions

This section summarizes how functions impact interrupt enables, system clock settings, and key hardware blocks
on the device. This information is provided such that the user will be able to consider the side effects of the API
functions.

6.1. Interrupt Priorities

The 8051 CPU has two priority levels. The user can specify priority level 0 or 1 for each interrupt source (each ISR
servicing an interrupt source) independently. After the reset all ISR routines are at lower priority level, priority level
0.
The interrupt priority levels are controlled by setting bits in the SFR registers IP and EIP1. Neither IP nor EIP1
registers are modified by any of the API functions. It is fully up to the user to specify the interrupt priorities. It is
recommended that it is done before calling any of the API functions.
The only system requirement related to the ISR is that the DMD ISR is present in the system. However, there is
another requirement related to the ISR priority levels:
The DMD ISR must be at the higher interrupt priority level than any function or ISR calling the following functions,
or which includes the software construct below. The items are the same as listed in the DMD ISR description
section above:
Functions which must be interruptible by the DMD ISR:
vFCast_Tune()
vSys_LpOscAdj()
vStl_PreLoop()
vStl_SingleTxLoop()
iMVdd_Measure()
Construct which must be interruptible by the DMD ISR:
while ( 0 == bDmdTx_GetSamplesTaken() ) {}
For example, if the vFCast_Tune() function is called from the RTC ISR, then the RTC interrupt must be set to be at
interrupt priority level 0 and the DMD interrupt must be set to be at priority 1, since DMD ISR must be able to
interrupt vFCast_Tune() function inside the RTC ISR.
If this requirement is not followed the system will stall. See "6.5. Infinite Loops" on page 27 for details.
It is recommended that the using 1 directive is used for all the ISR servicing interrupts at priority level 0, using 2
directive is used for all ISR servicing interrupts at priority level 1, and register bank 0 (RB0, which is the default
after reset) is used for main application.
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