Silicon Laboratories Si4010 Software Programming Manual page 93

GEN_DIV to its original value.
Overall system clock cycle count spent inside the function is determined by the following
expression:
Nclock_cycles = 32 + wiIntervalCount x 23
Since the function switches the internal system clock to the fastest speed, the actual delay
time depends on the current system clock speed the function was entered with. The actual
time spent inside of the function is:
T = 14 x T_clk_sys_entry + (18 + 23 x wiIntervalCount) x T_clk_sys_fast
where T_clk_sys_entry is the period of the system clock with which the function was
entered and T_clk_sys_fast is the clock period of the system clock with SYSCLK_DIV =
0 setting. Nominally, it is 1/24 MHz = 41.667 ns.
The longest delay this function can produce is 32 + 65535 * 23 = 1507337 cycles, result-
ing in 62.8 ms delay. The delay resolution is 23 cycles, corresponding to 0.958 µs.
The function does not disable any interrupts. It is fully interruptible. If the user does not
desire this function to be interrupted he has to disable the interrupts prior to calling this
function.
Inputs:
wiIntervalCount: (WORD) Determines the number of system clock cycles spent
inside of the function as shown in the expression above.
Outputs:
None
vSys_8BitDecLoop
Description: Implements software delay by waiting in a delay loop. This function sets the
SYSGEN_DIV field in the SYSGEN SFR to 0 forcing the fastest, 24MHz, system clock
frequency. Before returning, the function restores the SYSGEN_DIV to its original value.
Overall system clock cycle count spent inside of the function is determined by the follow-
ing expression:
Nclock_cycles = 35 + biIntervalCount x 10
Since the functions switches the internal system clock to the fastest speed, the actual delay
time depends on the current system clock speed the function was entered with. The actual
time spent inside of the function is:
T = 14 * T_clk_sys_entry + (21 + 10 x biIntervalCount) x T_clk_sys_fast
Rev. 1.0
AN370
93