Dut Socket; Pin Breakout - Xilinx Virtex-4 LX Prototype Platform User Manual

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12. DUT Socket

The DUT socket contains the user FPGA, referred to as the device under test (DUT). The
DUT must be oriented using the P1 indicator on the board.

13. Pin Breakout

The pin breakout area is used to monitor or apply signals to each of the DUT pins. Headers
can be soldered to the breakout area to use with certain types of oscilloscope probes, for
either connecting function generators or wiring pins to the pin breakout area. Clocks in the
pin breakout area that connect to the DUT clock pads are shown in
page
Table 8: Breakout Clock Pin Connections for SF363 and FF668
Virtex-4 LX/SX Prototype Platform
UG078 (v1.2) May 24, 2006
Caution!
Failure to insert the device to the proper orientation can damage the device. To avoid
pin damage, always use the vacuum tool provided when inserting or removing the Virtex-4
device. When using BGA packages, do not apply pressure to the device while activating the
socket. Doing so can damage the socket and/or the device.
20.
SF363
Label Clock Name
IO_L4P_GC_LC_3
IO_L4N_GC_VREF_LC_3
IO_L5P_GC_LC_3
IO_L5N_GC_LC_3
IO_L6P_GC_LC_3
IO_L6N_GC_LC_3
IO_L7P_GC_LC_3
IO_L7N_GC_LC_3
IO_L3P_GC_LC_3
IO_L3N_GC_LC_3
IO_L4P_GC_LC_4
IO_L4N_GC_VREF_LC_4
IO_L5P_GC_LC_4
IO_L5N_GC_LC_4
IO_L6P_GC_LC_4
IO_L6N_GC_LC_4
IO_L7P_GC_VRN_LC_4
IO_L7N_GC_VRP_LC_4
IO_L3P_GC_CC_LC_4
IO_L3N_GC_CC_LC_4
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Pin
Clock Name
Number
B10 IO_L4P_GC_LC_3
C10 IO_L4N_GC_VREF_LC_3
B13 IO_L5P_GC_LC_3
A13 IO_L5N_GC_LC_3
A8 IO_L6P_GC_LC_3
B8 IO_L6N_GC_LC_3
B14 IO_L7P_GC_LC_3
A14 IO_L7N_GC_LC_3
C11 IO_L3P_GC_LC_3
B11 IO_L3N_GC_LC_3
Y6 IO_L4P_GC_LC_4
W6 IO_L4N_GC_VREF_LC_4
W11 IO_L5P_GC_LC_4
W10 IO_L5N_GC_LC_4
Y7 IO_L6P_GC_LC_4
W7 IO_L6N_GC_LC_4
Y10 IO_L7P_GC_VRN_LC_4
Y9 IO_L7N_GC_VRP_LC_4
Y12 IO_L3P_GC_CC_LC_4
Y11 IO_L3N_GC_CC_LC_4
Detailed Description
Table 8 and Table 9,
FF668
Pin
Number
B13
B12
A16
A15
A10
B10
B17
A17
C14
C15
AF11
AF10
AE14
AE13
AE10
AD10
AD17
AD16
AB17
AC17
19