System Unit Block Diagram - Toshiba Tecra M1 Maintenance Manual

1.2 System Unit Block Diagram

– Integrated L2 cache memory: 1MB ECC protected cache data array, 8-way set
associative
– Integrated NDP
q Memory
Two BTO-compatible expansion memory slots are provided. Expansion up to 2GB (2,048MB) is
available.
DDR-SDRAM (Double Data Rate - Synchronous DRAM)
128 MB/256 MB/512 MB/1,024MB(1GB) selectable
– 128 MB (16M 16bit 4)
– 256 MB (16M 16bit 8)
– 512 MB (32M 8bit 16)
– 1,024MB (32M 16bit 8)
200 pin, SO Dual In-line Memory Modules (SO-DIMM)
2.5 volt operation
Supports DDR CL2/2.5
Supports PC2100 only
q Intel Odem (North Bridge)
One Intel 82845MP is used.
Features:
– Banias Processor System Bus Support
– DRAM Controller: DDR200/DDR266 Support, 1GB max
– Accelerated Graphics Port Interface: adheres to AGP2.0, AGP 4 mode
– Hub Link Interface
– 593-ball 37.5 37.5 mm FC-BGA package
q Intel ICH4-M (South Bridge)
One Intel 82801LAM is used.
This gate array has the following features:
– Hub Link Interface
– PCI Rev2.2 Interface (6 PCI REQ/GNT Pairs)
– BusMaster IDE Controller (Ultra ATA 100/66/33)
– USB 1.1/2.0 Controller 6 Prots (EHCI: Enhanced Host Controller)
– I/O APIC (ACPI 1.06)
– SMBus2.0 Controller
– FWH Interface (BIOS)
– LPC Interface (EC/KBC, Super I/O)
– IRQ Controller
– Serial Interrupt Controller
– Power Management Controller
TECRA M1 Maintenance Manual (960-436)
1 Hardware Overview
1-11