1. Manuals
  2. Brands
  3. GOWIN Manuals
  4. Motherboard
  5. DK-START-GW1NR9
  6. User manual

GOWIN DK-START-GW1NR9 User Manual

Hide thumbs Also See for DK-START-GW1NR9:
Table of Contents

Advertisement

Quick Links

Download this manual
DK-START-GW1NR9 V1.1
User Guide
DBUG361-1.2E, 2019/12/19

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the DK-START-GW1NR9 and is the answer not in the manual?

Questions and answers

Related Manuals for GOWIN DK-START-GW1NR9

Summary of Contents for GOWIN DK-START-GW1NR9

  • Page 1 DK-START-GW1NR9 V1.1 User Guide DBUG361-1.2E, 2019/12/19...
  • Page 2 Copyright 2019 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. © No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI.
  • Page 3 Revision History Date Version Description 03/19/2019 1.0E Initial version published. 11/29/2019 1.1E MIPI input function removed. 12/19/2019 1.2E The version of DK-START-GW1NR9 added.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................1 1.1 Purpose ..........................1 1.2 Supported Products ......................1 1.3 Related Documents ......................1 1.4 Terminology and Abbreviation .................... 2 1.5 Support and Feedback .......................
  • Page 5 3.8.1 Overview ........................21 3.8.2 GPIO Circuit ........................21 3.8.3 Pins Distribution ......................22 3.9 MIPI/LVDS ........................24 3.9.1 Overview ........................24 3.9.2 MIPI/LVDS Circuit ......................24 3.9.3 Pins Distribution ......................25 4 Precautions ....................29 5 Gowin YunYuan Software ................30 DBUG361-1.2E...

  • Page 6: List Of Figures

    List of Figures List of Figures Figure 2-1 DK-START-GW1NR9 V1.1 Development Board .............. 4 Figure 2-2 A Development Board Suite ..................... 5 Figure 2-3 PCB Components ......................6 Figure 2-4 System Diagram ....................... 7 Figure 3-1 GW1NR series FPGA Products I/O Bank Distribution ............. 12 Figure 3-2 GW1N-9 LQ144 Package Pins Distribution (Top View) ...........
  • Page 7 List of Tables List of Tables Table 1-1 Abbreviation and Terminology .................... 2 Table 2-1 Development Board Specification ..................9 Table 3-1 GW1NR-9 FPGA Resources List ..................11 Table 3-2 FPGA I/O Pins Distribution ....................13 Table 3-3 FPGA Download Pins Distribution ..................14 Table 3-4 FPGA Power Pins Distribution ...................

  • Page 8: About This Guide

    1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose The DK-START-GW1NR9 V1.1 user manual consists of the following four parts: 1. A brief introduction to the features and hardware resources of the development board; 2. An introduction to the function, circuit, and pin distribution of each module;...

  • Page 9: Terminology And Abbreviation

    1 About This Guide 1.4 Terminology and Abbreviation 1.4 Terminology and Abbreviation The terminology and abbreviation used in this manual are as shown in Table 1-1 below. Table 1-1 Abbreviation and Terminology Terminology and Abbreviation Meaning FPGA Field Programmable Gate Array System in Package SDRAM Synchronous Dynamic RAM...

  • Page 10: Support And Feedback

    1 About This Guide 1.5 Support and Feedback 1.5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com...

  • Page 11: Development Board Introduction

    Figure2-1 DK-START-GW1NR9 V1.1 Development Board The development board adopts the GW1NR-9 device, which is embedded with PSRAM of 64Mbit, user flash memory and other resources. The GW1NR series of FPGA products are the first generation of the Gowin ® LittleBee family and it is a SIP chip.

  • Page 12: A Development Board Suite

    LED, clock, reset and other resources for developers or fans to learn to use. 2.2 A Development Board Suite A development board suite includes the following items:  DK-START-GW1NR9 V1.1 Development Board  USB Cable  Quick Start Guide...

  • Page 13: Pcb Components

    2 Development Board Introduction 2.3 PCB Components 2.3 PCB Components Figure2-3 PCB Components 1.2V 3.3V 1.8V 2.5V LVDS LVDS FPGA Download 5V IN FPGA GPIO SWITCH RESET GPIO LVDS LVDS DBUG361-1.2E 6(30)

  • Page 14: System Diagram

    2 Development Board Introduction 2.4 System Diagram 2.4 System Diagram Figure2-4 System Diagram 4*BUTTON 4*SWITCH 4*LED 50MHz 10Pairs 10Pairs LVDS/MIPI LVDS/MIPI INPUT OUTPUT GW1NR- LV9LQ144P 20PIN 40PIN GPIO GPIO FPGA 1.2V/1.8V/2.5V/3.3V Mini USB Interface DBUG361-1.2E 7(30)

  • Page 15: Feature

    2 Development Board Introduction 2.5 Feature 2.5 Feature The structure and feature of the development board are as follows: 1. FPGA  LQFP144 package  Up to 120 user I/O  Embedded flash, data not easily lost if power down ...

  • Page 16: Development Board Specification

    2 Development Board Introduction 2.6 Development Board Specification 2.6 Development Board Specification Table 2-1 Development Board Specification Item Functional Description Technical Condition Remarks – – FPGA Core chip Support an USB – Download interface; Support USB to JTAG chip integrated on board JTAG, AUTOBOOT ...
  • Page 17 2 Development Board Introduction 2.6 Development Board Specification Item Functional Description Technical Condition Remarks Temperatur – Operating range: –20° ~70° – DBUG361-1.2E 10(30)

  • Page 18: Development Board Circuit

    3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module 3.1.1 Overview The resources of GW1NR series of FPGA products are shown in Table 3-1. Table 3-1 GW1NR-9 FPGA Resources List Device GW1NR-9 LUT4 8,640 Flip-Flop (FF) 6,480 Shadow SRAM 17,280...

  • Page 19: I/O Bank Introduction

    3 Development Board Circuit 3.1 FPGA Module 3.1.2 I/O BANK Introduction There are four I/O Banks in the GW1NR series of FPGA products, as shown in Figure 3-1. Figure 3-1 GW1NR series FPGA Products I/O Bank Distribution I/O BANK0 GW1NR I/O BANK2 DBUG361-1.2E 12(30)

  • Page 20: Figure3-2 Gw1N-9 Lq144 Package Pins Distribution (Top View)

    3 Development Board Circuit 3.1 FPGA Module Figure3-2 GW1N-9 LQ144 Package Pins Distribution (Top View) Table 3-2 FPGA I/O Pins Distribution I/O BANK No. Modules Connected  Pins selection for download mode  I/O BANK0 LVDS differential input  GPIO ...

  • Page 21: Download

    3 Development Board Circuit 3.2 Download 3.2 Download 3.2.1 Overview The development board provides an USB download interface. The data stream file can be downloaded to the internal SRAM, or internal flash as needed. Note!  When downloaded to SRAM, the data stream file will be lost if the device is powered down, and it will need to be downloaded again after power-on.

  • Page 22: Power Supply

    3 Development Board Circuit 3.3 Power Supply Signal Name Pin No. BANK Description I/O Level FTDI JTAG Signal 1.8V TCK_ FTDI JTAG Signal 1.8V TDI_ FTDI JTAG Signal 1.8V TDO_ Mode selection MODE0 2.5V Mode selection MODE1 2.5V RECONFIG_N RECONFIG_N 1.8V One DONE DONE...

  • Page 23: Power System Distribution

    3 Development Board Circuit 3.3 Power Supply 3.3.2 Power System Distribution Figure3-4 Power System Distribution USB Interface DC5V Input USB to JTAG （FT2232） TPS7A7001 3.3V Key&LED&Reset& switch FPGA VCCO2 (LVDS) TPS7A7001 FPGA 2.5V VCCX&VCCO0 &VCCO1 TPS7A7001 FPGA VCCO3 (PSRAM) 1.8V FPGA VCCO2 (MIPI) TPS7A7001...

  • Page 24: Clock, Reset

    3 Development Board Circuit 3.4 Clock, Reset Signal Name Pin No. BANK Description I/O Level I/O Bank VCCO2 37, 55 2.5V/1.2V Voltage I/O Bank VCCO3 9, 19 1.8V Voltage Auxiliary VCCX 31, 77 2.5V voltage 1, 36, 73, 108 Core voltage 1.2V 2, 17, 33, 35, 53, 74, 89, 105, 107...

  • Page 25: Led

    3 Development Board Circuit 3.5 LED 3.5 LED 3.5.1 Overview There are four green LEDs in the development board and users can display the required status through the LED. There are two LEDs left to facilitate the observation of power supply and FPGA loading status. Users can test the LEDs in the following ways: ...

  • Page 26: Switches

    3 Development Board Circuit 3.6 Switches 3.6 Switches 3.6.1 Overview There are four slide switches in the development board to control input during testing. 3.6.2 Switch Circuit Figure3-7 Switch Circuit VCC3P3 F_SW1 F_SW2 GW1NR- F_SW3 LV9LQ144P F_SW4 3.6.3 Pins Distribution Table 3-7 Switch Circuit Pins Distribution Signal Name Pin No.

  • Page 27: Key

    3 Development Board Circuit 3.7 Key 3.7 Key 3.7.1 Overview There are four key switches in the development board. Users can manually input low level to the corresponding FPGA pins for testing purposes. 3.7.2 Key Circuit Figure3-8 Key Circuit Diagram VCC3P3 KEY1 F_KEY1...

  • Page 28: Gpio

    3 Development Board Circuit 3.8 GPIO 3.8 GPIO 3.8.1 Overview One 2.54mm DC3-20P socket and one 2.54mm DC3-40P socket are reserved in the development board to facilitate the users to do the function expansion and testing. 3.8.2 GPIO Circuit Figure3-9 GPIO Circuit H_B_IO1 H_B_IO2 H_B_IO4...

  • Page 29: Pins Distribution

    3 Development Board Circuit 3.8 GPIO 3.8.3 Pins Distribution Table 3-9 J14 GPIO Pins Distribution Signal Name Pin No. Socket Pin No. BANK Description I/O Level H_A_IO1 General I/O 1.8V H_A_IO2 General I/O 1.8V H_A_IO3 General I/O 1.8V H_A_IO4 General I/O 1.8V H_A_IO5 General I/O...
  • Page 30 3 Development Board Circuit 3.8 GPIO Signal Name Pin No. Socket Pin No. BANK Description I/O Level H_B_IO10 General I/O 2.5V H_B_IO11 General I/O 2.5V H_B_IO12 General I/O 2.5V H_B_IO13 General I/O 2.5V H_B_IO14 General I/O 2.5V H_B_IO15 General I/O 2.5V H_B_IO16 General I/O...

  • Page 31: Mipi/Lvds

    3 Development Board Circuit 3.9 MIPI/LVDS 3.9 MIPI/LVDS 3.9.1 Overview Two 2 mm DC3-20P sockets are reserved in the development board for MIPI/LVDS input/output performance testing and high-speed data transmission. Up to 10 pairs of differential input and 10 pairs of differential output can be satisfied.

  • Page 32: Pins Distribution

    3 Development Board Circuit 3.9 MIPI/LVDS 3.9.3 Pins Distribution Table 3-11 J15 FPGA Pin Distribution (IDES16:1 Supported) Signal Name Pin No. Socket Pin No. BANK Description I/O Level Differential input F_LVDS_A1_P channel 1+ 2.5V(LVDS) Differential input F_LVDS_A1_N channel 1- 2.5V(LVDS) Differential input F_LVDS_A2_P channel 2+...
  • Page 33 3 Development Board Circuit 3.9 MIPI/LVDS Signal Name Pin No. Socket Pin No. BANK Description I/O Level channel 6- Differential input F_LVDS_A7_P channel 7+ 2.5V(LVDS) Differential input F_LVDS_A7_N channel 7- 2.5V(LVDS) Differential input F_LVDS_A8_P channel 8+ 2.5V(LVDS) Differential input F_LVDS_A8_N channel 8- 2.5V(LVDS) Differential input...

  • Page 34: Table 3-13 J16 Fpga Pin Distribution (Ides16:1 Supported)

    3 Development Board Circuit 3.9 MIPI/LVDS Table 3-13 J16 FPGA Pin Distribution (IDES16:1 Supported) Signal Name Pin No. Socket Pin No. BANK Description I/O Level Differential output channel 2.5V(LVDS)/ F_LVDS_B1_P 1.2V(MIPI) Differential output channel 2.5V(LVDS)/ F_LVDS_B1_N 1.2V(MIPI) Differential output channel 2.5V(LVDS)/ F_LVDS_B2_P 1.2V(MIPI)

  • Page 35: Table 3-14 J18 Fpga Pin Distribution (Ides16:1 Supported)

    3 Development Board Circuit 3.9 MIPI/LVDS Signal Name Pin No. Socket Pin No. BANK Description I/O Level Table 3-14 J18 FPGA Pin Distribution (IDES16:1 Supported) Signal Name Pin No. Socket Pin No. BANK Description I/O Level Differential output 2.5V(LVDS)/ F_LVDS_B6_P channel 6+ 1.2V(MIPI) Differential output...

  • Page 36: Precautions

    4 Precautions Precautions Attentions in use of the development board: 1. Handle with care and pay attention to electrostatic protection; 2. VCCO2 Bank voltage needs to be set as 2.5V when the Bank2 output differential pairs serve as LVDS output; VCCO2 Bank voltage needs to be set as 1.2V when the Bank2 output differential pairs serve as MIPI output.

  • Page 37: Gowin Yunyuan Software

    5 Gowin YunYuan Software Gowin YunYuan Software Please refer to SUG100, Gowin Software User Guide for details. DBUG361-1.2E 30(30)

Table of Contents