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GOWIN DK-START-GW1NR9 User Manual

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DK-START-GW1NR9 V1.1
User Guide
DBUG361-1.3E, 2021/08/20

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Summary of Contents for GOWIN DK-START-GW1NR9

  • Page 1 DK-START-GW1NR9 V1.1 User Guide DBUG361-1.3E, 2021/08/20...
  • Page 2 Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Version Description 03/19/2019 1.0E Initial version published. 11/29/2019 1.1E MIPI input function removed. 12/19/2019 1.2E The version of DK-START-GW1NR9 added.  The Quick Start in 2.2 A Development Board Suite removed; 08/20/2021 1.3E  The Chapter 6 Quick Start added.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 1 1.4 Support and Feedback ....................... 2 2 Development Board Introduction ..............
  • Page 5 3.8.2 GPIO Circuit ........................17 3.8.3 Pinout ..........................18 3.9 MIPI/LVDS ........................20 3.9.1 Overview ........................20 3.9.2 MIPI/LVDS Circuit ......................20 3.9.3 Pinout ..........................21 4 Considerations .................... 25 5 Gowin Software ................... 26 6 Quick Start ....................27 DBUG361-1.3E...

  • Page 6: List Of Figures

    List of Figures List of Figures Figure 2-1 DK-START-GW1NR9 V1.1 Development Board .............. 3 Figure 2-2 A Development Board Suite11 ..................4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Diagram ....................... 5 Figure 3-1 GW1NR series FPGA Products I/O Bank Distribution ............. 10 Figure 3-2 GW1N-9 LQ144 Package Pins Distribution (Top View) ...........
  • Page 7 List of Tables List of Tables Table 1-1 Abbreviation and Terminology .................... 2 Table 2-1 Development Board Specification ..................7 Table 3-1 GW1NR-9 FPGA Resources List ..................9 Table 3-2 FPGA I/O Pinout ......................... 11 Table 3-3 FPGA Download Pinout ..................... 12 Table 3-4 FPGA Power Pinout ......................

  • Page 8: About This Guide

    1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose The DK-START-GW1NR9 V1.1 user manual consists of the following four parts: 1. A brief introduction to the features and hardware resources of the development board; 2. An introduction to the function, circuit, and pin distribution of each module;...

  • Page 9: Support And Feedback

    Phase-locked Loop Delay-locked Loop LQ144 LQFP144 package 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...

  • Page 10: Development Board Introduction

    Figure 2-1 DK-START-GW1NR9 V1.1 Development Board The development board adopts the GW1NR-9 device, which is embedded with PSRAM of 64Mbit, user flash memory and other resources. The GW1NR series of FPGA products are the first generation of the Gowin ® LittleBee family and it is a SIP chip.

  • Page 11: A Development Board Suite

    2 Development Board Introduction 2.2 A Development Board Suite 2.2 A Development Board Suite A development board suite includes the following items: DK-START-GW1NR9 V1.1 Development Board  USB Cable  Figure 2-2 A Development Board Suite ① DK-START-GW1NR9 V1.1 Development Board ②...

  • Page 12: Pcb Components

    2 Development Board Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components 2.5V 1.2V 3.3V LVDS 1.8V LVDS FPGA Download 5V IN FPGA GPIO Switch Reset GPIO LVDS LVDS 2.4 System Diagram Figure 2-4 System Diagram 4*BUTTON 4*SWITCH 4*LED 50MHz 10Pairs...

  • Page 13: Feature

    2 Development Board Introduction 2.5 Feature 2.5 Feature The structure and feature of the development board are as follows: 1. FPGA LQFP144 package  Up to 120 user I/O  Embedded flash, data not easily lost if power down  Abundant LUT4 resources ...

  • Page 14: Development Board Specification

    2 Development Board Introduction 2.6 Development Board Specification 2.6 Development Board Specification Table 2-1 Development Board Specification Item Functional Description Technical Condition Note – – FPGA Core chip Support an USB USB to JTAG chip – Download interface; Support integrated on board JTAG, AUTOBOOT ...
  • Page 15 2 Development Board Introduction 2.6 Development Board Specification Item Functional Description Technical Condition Note discharge; over current protection Schottky diode is  connected between positive and negative anodes of power interface;  2A self-recovery fuses are connected at power inlet –...

  • Page 16: Development Board Circuit

    3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module 3.1.1 Overview The resources of GW1NR series of FPGA products are shown in Table 3-1. Table 3-1 GW1NR-9 FPGA Resources List Device GW1NR-9 LUT4 8,640 Flip-Flop (FF) 6,480 Shadow SRAM 17,280...

  • Page 17: Figure 3-1 Gw1Nr Series Fpga Products I/O Bank Distribution

    3 Development Board Circuit 3.1 FPGA Module Figure 3-1 GW1NR series FPGA Products I/O Bank Distribution Figure 3-2 GW1N-9 LQ144 Package Pins Distribution (Top View) DBUG361-1.3E 10(27)

  • Page 18: Download

    3 Development Board Circuit 3.2 Download Table 3-2 FPGA I/O Pinout I/O BANK No. Modules Connected  Pins selection for download mode I/O BANK0  LVDS differential input  GPIO  GPIO  50MHz clock input  I/O BANK1  Slide Switches ...

  • Page 19: Download Flow

    3 Development Board Circuit 3.3 Power Supply 3.2.3 Download Flow Please plug USB download cable into the USB interface (J6) of the development board to download FPGA, and then open Programmer, click SRAM mode or Embedded flash mode to download bit stream file to SRAM or flash.

  • Page 20: Pinout

    3 Development Board Circuit 3.3 Power Supply Figure 3-4 Power System Distribution USB Interface DC5V Input USB to JTAG （FT2232） TPS7A7001 3.3V Key&LED&Reset& switch FPGA VCCO2 (LVDS) TPS7A7001 FPGA 2.5V VCCX&VCCO0 &VCCO1 TPS7A7001 FPGA VCCO3 (PSRAM) 1.8V FPGA VCCO2 (MIPI) TPS7A7001 1.2V FPGA VCC...

  • Page 21: Clock, Reset

    3 Development Board Circuit 3.4 Clock, Reset 3.4 Clock, Reset 3.4.1 Overview The development board provides a 50MHz crystal oscillator connected to the PLL input pin. This can be employed as the input clock for the PLL in FPGA. Frequency division and multiplication of PLL can output the clock required by the user.

  • Page 22: Led Circuit

    3 Development Board Circuit 3.6 Switches 3.5.2 LED Circuit Figure 3-6 LED Circuit 3.5.3 Pinout Table 3-6 LED Pinout Signal Name Pin No. BANK Description I/O Level F_LED1 LED1 2.5V F_LED2 LED2 2.5V F_LED3 LED3 2.5V F_LED4 JESD 4 2.5V 3.6 Switches 3.6.1 Overview There are four slide switches in the development board to control input...

  • Page 23: Pinout

    3 Development Board Circuit 3.7 Key 3.6.3 Pinout Table 3-7 Switch Circuit Pinout Signal Name Pin No. BANK Description I/O Level F_SW1 Slide Switch1 2.5V F_SW2 Slide Switch2 2.5V F_SW3 Slide Switch3 2.5V F_SW4 Slide Switch2 2.5V 3.7 Key 3.7.1 Overview There are four key switches in the development board.

  • Page 24: Gpio

    3 Development Board Circuit 3.8 GPIO 3.8 GPIO 3.8.1 Overview One 2.54mm DC3-20P socket and one 2.54mm DC3-40P socket are reserved in the development board to facilitate the users to do the function expansion and testing. 3.8.2 GPIO Circuit Figure 3-9 GPIO Circuit H_B_IO1 H_B_IO2 H_B_IO4...

  • Page 25: Pinout

    3 Development Board Circuit 3.8 GPIO 3.8.3 Pinout Table 3-9 J14 GPIO Pinout Signal Name Pin No. Socket Pin No. BANK Description I/O Level H_A_IO1 General I/O 1.8V H_A_IO2 General I/O 1.8V H_A_IO3 General I/O 1.8V H_A_IO4 General I/O 1.8V H_A_IO5 General I/O 1.8V...
  • Page 26 3 Development Board Circuit 3.8 GPIO Signal Name Pin No. Socket Pin No. BANK Description I/O Level H_B_IO11 General I/O 2.5V H_B_IO12 General I/O 2.5V H_B_IO13 General I/O 2.5V H_B_IO14 General I/O 2.5V H_B_IO15 General I/O 2.5V H_B_IO16 General I/O 2.5V H_B_IO17 General I/O...

  • Page 27: Mipi/Lvds

    3 Development Board Circuit 3.9 MIPI/LVDS 3.9 MIPI/LVDS 3.9.1 Overview Two 2 mm DC3-20P sockets are reserved in the development board for MIPI/LVDS input/output performance testing and high-speed data transmission. Up to 10 pairs of differential input and 10 pairs of differential output can be satisfied.

  • Page 28: Pinout

    3 Development Board Circuit 3.9 MIPI/LVDS 3.9.3 Pinout Table 3-11 J15 FPGA Pinout (IDES16:1 Supported) Socket Signal Name Pin No. BANK Description I/O Level Pin No. Differential input F_LVDS_A1_P 2.5V(LVDS) channel 1+ Differential input F_LVDS_A1_N 2.5V(LVDS) channel 1- Differential input F_LVDS_A2_P 2.5V(LVDS) channel 2+...

  • Page 29: Table 3-12 J17 Fpga Pinout

    3 Development Board Circuit 3.9 MIPI/LVDS Table 3-12 J17 FPGA Pinout Socket Signal Name Pin No. BANK Description I/O Level Pin No. Differential input F_LVDS_A6_P 2.5V(LVDS) channel 6+ Differential input F_LVDS_A6_N 2.5V(LVDS) channel 6- Differential input F_LVDS_A7_P 2.5V(LVDS) channel 7+ Differential input F_LVDS_A7_N 2.5V(LVDS)

  • Page 30: Table 3-13 J16 Fpga Pinout (Ides16:1 Supported)

    3 Development Board Circuit 3.9 MIPI/LVDS Table 3-13 J16 FPGA Pinout (IDES16:1 Supported) Socket Signal Name Pin No. BANK Description I/O Level Pin No. Differential output 2.5V(LVDS)/ F_LVDS_B1_P channel 1+ 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_B1_N channel 1- 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_B2_P channel 2+...

  • Page 31: Table 3-14 J18 Fpga Pinout (Ides16:1 Supported)

    3 Development Board Circuit 3.9 MIPI/LVDS Table 3-14 J18 FPGA Pinout (IDES16:1 Supported) Socket Signal Name Pin No. BANK Description I/O Level Pin No. Differential output 2.5V(LVDS)/ F_LVDS_B6_P channel 6+ 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_B6_N channel 6- 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_B7_P channel 7+...

  • Page 32: Considerations

    4 Considerations Considerations Considerations for the use of the development board: 1. Handle with care and pay attention to electrostatic protection; 2. VCCO2 Bank voltage needs to be set as 2.5V when the Bank2 output differential pairs serve as LVDS output; VCCO2 Bank voltage needs to be set as 1.2V when the Bank2 output differential pairs serve as MIPI output.

  • Page 33: Gowin Software

    5 Gowin Software Gowin Software See SUG100, Gowin Software User Guide for details. DBUG361-1.3E 26(27)

  • Page 34: Quick Start

    6 Quick Start Quick Start See TN436, DK-START-GW1NR9 Development Board Quick Start User Guide for details. DBUG361-1.3E 27(27)

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