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Summary of Contents for GOWIN DK-NANO-GW2A55-PG484
- Page 1 DK-NANO-GW2A55-PG484 V1.1DK-NANO-GW2A55-PG484 V1.1 User Guide DBUG374-1.0E,07/27/2020...
- Page 2 Copyright© 2020 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer ®...
- Page 3 Revision History Date Version Description 07/27/2020 1.0E Initial version published.
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Page 4: Table Of Contents
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Supported Products ......................1 1.3 Related Documents ......................1 1.4 Terminology and Abbreviations ................... 2 1.5 Support and Feedback ....................... - Page 5 Contents 3.5.1 Introduction ........................11 3.5.2 Pinout ..........................12 3.6 MIPI DSI ........................... 14 3.6.1 Introduction ........................14 3.6.2 Pinout ..........................15 3.7 MIPI CSI ........................... 17 3.7.1 Introduction ........................17 3.7.2 Pinout ..........................18 3.8 GPIO ..........................21 3.8.1 Introduction ........................21 3.8.2 Pinout ..........................
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Page 6: List Of Figures
List of Figures List of Figures Figure 2-1 DK-NANO-GW2A55-PG484 V1.1 ..................3 Figure 2-2 A Development Kit ......................4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Block Diagram ..................... 6 Figure 3-1 Connection Diagram of FPGA Downloading and Configuration ........9 Figure 3-2 Asynchronous FIFO Connection Diagram ................ - Page 7 List of Tables List of Tables Table 1-1 Terminology and Abbreviations ..................2 Table 3-1 FPGA Pinout ........................9 Table 3-2 Clock and Reset Pinout...................... 11 Table 3-3 LVDS TX0 Interface Pinout ....................12 Table 3-4 LVDS TX Interface Pinout ....................13 Table 3-5 LVDS RX0 Interface Pinout ....................
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Page 8: About This Guide
1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose The DK-NANO-GW2A55-PG484 V1.1 development board (hereinafter referred to development board) user guide consists of the following four parts: 1. A brief introduction to the features of the development board;... -
Page 9: Terminology And Abbreviations
Low-Voltage Differential Signaling S-SRAM Shadow Static Random Access Memory 1.5 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com... -
Page 10: Introduction
The development board uses the GW2A- LV55PG484 FPGA device, which is the first generation of Gowin Arora family. The GW2A series of FPGA products offer abundant resources like high-performance DSP, high-speed LVDS interface and BSRAM. These embedded resources... -
Page 11: Development Kit
FLASH chip is used to store FPGA configuration programs. There are switches, keys, LEDs and buzzer that you can use to debug. 2.2 Development Kit The development board kit includes the following items: DK-NANO-GW2A55-PG484 V1.1 5V power (Input: 100-240V~50/60Hz 0.5A, output: DC 5V 2A) Mini-USB Cable ... -
Page 12: Pcb Components
2Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components 64Mbit LVDS TX1 Flash MIPI TX1 GPIO0 Buzzer LVDS RX1 MIPI RX1 GW2A55-PG484 LED*4 MIPI RX0 Key*4 LVDS RX0 MINI B Switch*2 GPIO1 MIPI TX0 USB to JTAG LVDS TX0 Chip DBUG374-1.0E 5(28) -
Page 13: System Block Diagram
MINI USB 2.5 Features The key features are as follows: 1. The FPGA device Gowin GW2A-LV55PG484 FPGA Up to 319 user I/O 2. Download and Boot The download module is integrated on the board and you can use the USB Mini B cable to download FPGA. - Page 14 2 Introduction 2.5 Features The development board can generate 3.3V, 2.5V, 1.2V, 1.0V. 4. Clock system 50MHz crystal oscillator input 5. Memory Device 64Mbit FLASH 6. LVDS Interfaces Two LVDS interfaces for receiving, including ten pairs of differential signals.
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Page 15: Development Board Circuit
Development Board Circuit 3.1 FPGA Module Overview For the resources of GW2A series of FPGA Products, please refer to DS102, GW2A series of FPGA products. I/O BANK Introduction For the I/O BANK, package and pinout information, see UG111, GW2A series of FPGA Products Package and Pinout User Guide for more details. 3.2 Download Module 3.2.1 Introduction The development board provides USB download interface, which is... -
Page 16: Pinout
3 Development Board Circuit 3.2 Download Module Figure 3-1 Connection Diagram of FPGA Downloading and Configuration JTAG_TCK USB_D+ JTAG_TDO USB_D- USB to JTAG JTAG_TDI Chip JTAG_TMS FLASH_SPI_MISO FLASH_SPI_MOSI Configure FLASH_SPI_CS_N FLASH FLASH_SPI_CLK By configuring EEPROM chip, the B channel of FT2232 can be configured as an asynchronous FIFO interface. -
Page 17: Power Supply
3 Development Board Circuit 3.3 Power Supply Name FPGA Pin No. BANK I/O Level Description Configure FLASH FLASH_SPI_MISO 1.5V Signal Configure FLASH FLASH_SPI_MOSI 1.5V Signal Configure FLASH FLASH_SPI_CS_N 1.5V Signal Configure FLASH FLASH_SPI_CLK 1.5V Signal 3.3 Power Supply 3.3.1 Introduction The development board is powered via a power adapter. -
Page 18: Pinout
3 Development Board Circuit 3.5 LVDS Interfaces 3.4.2 Pinout Table 3-2 Clock and Reset Pinout Name FPGA Pin No. BANK I/O Level Description CLK_G 3.3V 50MHz crystal oscillator input 3.5 LVDS Interfaces 3.5.1 Introduction The LVDS interfaces are the four 20 pins with the pitch of 2.00mm, of which two are transmitting interface, and the other are receiving interface. -
Page 19: Pinout
3 Development Board Circuit 3.5 LVDS Interfaces Figure 3-5 LVDS RX Interface LVDS_RX1_D0p LVDS_RX0_D0p LVDS_RX0_D0n LVDS_RX1_D0n LVDS_RX0_D1n LVDS_RX1_D1n LVDS_RX0_D1p LVDS_RX1_D1p LVDS_RX0_D2p LVDS_RX0_D2n LVDS_RX1_D2n LVDS_RX1_D2p LVDS_RX0_D3p LVDS_RX0_D3n LVDS_RX1_D3n LVDS_RX1_D3p LVDS_RX0_D4n LVDS_RX1_D4n LVDS_RX0_D4p LVDS_RX1_D4p 3.5.2 Pinout Table 3-3 LVDS TX0 Interface Pinout Name FPGA Pin No. -
Page 20: Table 3-4 Lvds Tx Interface Pinout
3 Development Board Circuit 3.5 LVDS Interfaces Table 3-4 LVDS TX Interface Pinout Name FPGA Pin No. BANK I/O Level Description Differential LVDS_TX1_D0p 2.5V Channel 6+ Differential LVDS_TX1_D0n 2.5V Channel 6- Differential LVDS_TX1_D1p 2.5V Channel 7+ Differential LVDS_TX1_D1n 2.5V Channel 7- Differential LVDS_TX1_D2p 2.5V... -
Page 21: Mipi Dsi
3 Development Board Circuit 3.6 MIPI DSI Name FPGA Pin No. BANK I/O Level Description Differential LVDS_RX0_D4n 2.5V Channel 5- Table 3-6 LVDS RX1 Interface Pinout Name FPGA Pin No. BANK I/O Level Description Differential LVDS_RX1_D0p 2.5V Channel 6+ Differential LVDS_RX1_D0n 2.5V Channel 6-... -
Page 22: Pinout
3 Development Board Circuit 3.6 MIPI DSI Figure 3-6 MIPI DSI TX0 Diagram MIMP_TX0_D0p MIMP_TX0_LP_D0p MIMP_TX0_D0p MIMP_TX0_D0n MIMP_TX0_LP_D0n MIMP_TX0_D0n MIMP_TX0_D1p MIMP_TX0_D1n MIMP_TX0_LP_D1p MIMP_TX0_D1p MIMP_TX0_LP_D1n MIMP_TX0_D1n MIMP_TX0_CLKp MIMP_TX0_CLKn MIMP_TX0_LP_CLKp MIMP_TX0_CLKp MIMP_TX0_D2p MIMP_TX0_D2n MIMP_TX0_LP_CLKn MIMP_TX0_CLKn MIMP_TX0_D3p MIMP_TX0_LP_D2p MIMP_TX0_D2p MIMP_TX0_D3n MIMP_TX0_LP_D2n MIMP_TX0_D2n MIMP_TX0_LP_D3p MIMP_TX0_D3p MIMP_TX0_LP_D3n MIMP_TX0_D3n... -
Page 23: Table 3-8 Mipi Dsi Tx1 Pinout
3 Development Board Circuit 3.6 MIPI DSI Name FPGA Pin No. BANK I/O Level Description MIPI_TX0_D2n 2.5V HS differential data 2- MIPI_TX0_D2p 2.5V HS differential data 2+ MIPI_TX0_D3n 2.5V HS differential data 3- MIPI_TX0_D3p 2.5V HS differential data 3+ MIPI_TX0_LP_D0n 1.2V LP single-ended data 0 MIPI_TX0_LP_D0p... -
Page 24: Mipi Csi
3 Development Board Circuit 3.7 MIPI CSI Name FPGA Pin No. BANK I/O Level Description MIPI_TX1_LP_C 1.2V LP single-ended clock MIPI_TX1_LP_D 1.2V LP single-ended data 2 MIPI_TX1_LP_D 1.2V LP single-ended data 2 MIPI_TX1_LP_D 1.2V LP single-ended data 3 MIPI_TX1_LP_D 1.2V LP single-ended data 3 3.7 MIPI CSI 3.7.1 Introduction... -
Page 25: Pinout
3 Development Board Circuit 3.7 MIPI CSI Figure 3-9 Connection Diagram of MIPI CSI RX1 MIPI_RX1_D0p MIPI_RX1_LP_D0p MIPI_RX1_D0p MIPI_RX1_D0n MIPI_RX1_LP_D0n MIPI_RX1_D0n MIPI_RX1_D1p MIPI_RX0_D1n MIPI_RX1_LP_D1p MIPI_RX1_D1p MIPI_RX1_LP_D1n MIPI_RX1_D1n MIPI_RX1_CLKp MIPI_RX1_CLKn MIPI_RX1_LP_CLKp MIPI_RX1_CLKp MIPI_RX1_LP_CLKn MIPI_RX1_CLKn MIPI_RX1_D2p MIPI_RX1_D2n MIPI_RX1_LP_D2p MIPI_RX1_D2p MIPI_RX1_D3p MIPI_RX1_LP_D2n MIPI_RX1_D2n MIPI_RX1_D3n MIPI_RX1_LP_D3p MIPI_RX1_D3p... - Page 26 3 Development Board Circuit 3.7 MIPI CSI Name FPGA Pin No. BANK I/O Level Description HS differential MIPI_RX0_D0n 2.5V data 0- HS differential MIPI_RX0_D1p 2.5V data 1+ HS differential MIPI_RX0_D1n 2.5V data 1 MIPI_RX0_CLK HS Differential 2.5V clock+ MIPI_RX0_CLK HS Differential 2.5V clock- HS differential...
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Page 27: Table 3-10 Mipi Csi Rx1 Pinout
3 Development Board Circuit 3.7 MIPI CSI Table 3-10 MIPI CSI RX1 Pinout Name FPGA Pin No. BANK I/O Level Description HS differential MIPI_RX1_D0p 2.5V data 0+ HS differential MIPI_RX1_D0n 2.5V data 0- HS differential MIPI_RX1_D1p 2.5V data 1+ HS differential MIPI_RX1_D1n 2.5V data 1... -
Page 28: Gpio
3 Development Board Circuit 3.8 GPIO Name FPGA Pin No. BANK I/O Level Description CLKn clock 3.8 GPIO 3.8.1 Introduction 70 GPIOs channeled by two double-column pins with 2.54mm pitch are reserved on the development board for testing. GPIO of two 40pin interfaces multiplex. -
Page 29: Pinout
3 Development Board Circuit 3.8 GPIO Figure 3-11 Diagram of 40pin GPIO1 3.3V GPIO1_0 GPIO1_1 GPIO1_2 GPIO1_3 GPIO1_4 GPIO1_5 GPIO1_6 GPIO1_7 GPIO1_8 GPIO1_9 GPIO1_11 GPIO1_10 GPIO1_13 GPIO1_12 GPIO1_14 GPIO1_15 GPIO1_17 GPIO1_16 GPIO1_18 GPIO1_19 GPIO1_21 GPIO1_20 GPIO1_22 GPIO1_23 GPIO1_24 GPIO1_25 GPIO1_27 GPIO1_26 GPIO1_28 GPIO1_29... -
Page 30: Table 3-12 40Pin Gpio1 Pinout
3 Development Board Circuit 3.8 GPIO Name FPGA Pin No. BANK I/O Level Description 3.3V General I/O GPIO0_6 3.3V General I/O GPIO0_7 3.3V General I/O GPIO0_8 3.3V General I/O GPIO0_9 3.3V General I/O GPIO0_10 3.3V General I/O GPIO0_11 3.3V General I/O GPIO0_12 3.3V General I/O... -
Page 31: Led Indicators Module
3 Development Board Circuit 3.9 LED Indicators Module Name FPGA Pin No. BANK I/O Level Description 3.3V General I/O GPIO1_5 3.3V General I/O GPIO1_6 3.3V General I/O GPIO1_7 3.3V General I/O GPIO1_8 3.3V General I/O GPIO1_9 3.3V General I/O GPIO1_10 3.3V General I/O GPIO1_11... -
Page 32: Pinout
3 Development Board Circuit 3.10 Keys Module Figure 3-12 LED Diagram 3.3V LED1 LED2 LED3 LED4 3.9.2 Pinout Table 3-13 LED Indicator Pinout Name FPGA Pin No. BANK I/O Level Description LED1 3.3V LED 1 LED2 3.3V LED 2 LED3 3.3V LED 3 LED4... -
Page 33: Pinout
3 Development Board Circuit 3.11 Switches Module Figure 3-13 Key Circuit Diagram AB21 KEY1 KEY2 AA22 KEY3 KEY4 3.10.2 Pinout Table 3-14 Keys Pinout Name FPGA Pin No. BANK I/O Level Description KEY1 3.3V KEY1 AB21 KEY2 3.3V KEY2 KEY3 3.3V KEY3 AA22... -
Page 34: Pinout
3 Development Board Circuit 3.12 LED Display Module Figure 3-14 Switch Circuit Diagram 3.3V AA21 3.11.2 Pinout Table 3-15 Switches Pinout Name FPGA Pin No. BANK I/O Level Description 3.3V Switch1 3.3V Switch2 AA21 3.12 LED Display Module 3.12.1 Introduction There is a two-digit LED on the development board to control output during testing. -
Page 35: Pinout
3 Development Board Circuit 3.13 Buzzer Module 3.12.2 Pinout Table 3-16 Switches Pinout Name FPGA Pin No. BANK I/O Level Description DS-a1 3.3V DS-b1 3.3V DS-c1 3.3V DS-d1 3.3V DS-e1 3.3V DS-f1 3.3V DS-g1 3.3V DS-dp1 3.3V DS-D-A1 3.3V Driver control DS-D-A2 3.3V Driver control...
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