GOWIN DK-START-GW1NR9 V2.1 User Manual
  1. Manuals
  2. Brands
  3. GOWIN Manuals
  4. Motherboard
  5. DK-START-GW1NR9 V2.1
  6. User manual

GOWIN DK-START-GW1NR9 V2.1 User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
DK-START-GW1NR9 V2.1
User Guide
DBUG384-1.3E, 2021/08/24

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the DK-START-GW1NR9 V2.1 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for GOWIN DK-START-GW1NR9 V2.1

Summary of Contents for GOWIN DK-START-GW1NR9 V2.1

  • Page 1 DK-START-GW1NR9 V2.1 User Guide DBUG384-1.3E, 2021/08/24...
  • Page 2 Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 12/19/2019 1.0E Initial version published. 03/17/2020 1.1E Picture of development board updated. 04/08/2020 1.2E The number of MIPI output updated.  The Quick Start in 2.2 A Development Board Suite removed; 08/24/2021 1.3E  The chapter 6 Quick Start added.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviation .................... 1 1.4 Support and Feedback ....................... 2 2 Development Board Introduction ..............
  • Page 5 3.8.2 GPIO Circuit ........................18 3.8.3 Pinout ..........................19 3.9 MIPI/LVDS ........................21 3.9.1 Overview ........................21 3.9.2 MIPI/LVDS Circuit ......................21 3.9.3 Pinout ..........................22 4 Considerations .................... 25 5 Gowin Software ................... 26 6 Quick Start ....................27 DBUG384-1.3E...

  • Page 6: List Of Figures

    List of Figures List of Figures Figure 2-1 DK-START-GW1NR9 V2.1 Development Board .............. 3 Figure 2-2 A Development Board Suite ..................... 4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Diagram ....................... 5 Figure 3-1 GW1NR series FPGA Products I/O Bank Distribution ............. 10 Figure 3-2 GW1NR-9 LQ144 Package Pinout (Top View) ..............
  • Page 7 List of Tables List of Tables Table 1-1 Abbreviation and Terminology .................... 2 Table 2-1 Development Board Specification ..................7 Table 3-1 GW1NR-9 FPGA Resources List ..................9 Table 3-2 FPGA I/O Pinout ......................... 11 Table 3-3 FPGA Download Pinout ..................... 12 Table 3-4 FPGA Power Pinout ......................

  • Page 8: About This Guide

    1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose The DK-START-GW1NR9 V2.1 user manual consists of the following four parts: 1. A brief introduction to the features and hardware resources of the development board; 2. An introduction to the function, circuit, and pinout of each module;...

  • Page 9: Support And Feedback

    Phase-locked Loop Delay-locked Loop LQ144 LQFP144 package 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com E-mail: support@gowinsemi.com...

  • Page 10: Development Board Introduction

    Figure 2-1 DK-START-GW1NR9 V2.1 Development Board The development board adopts the GW1NR-9 device, which is embedded with PSRAM of 64Mbit, user flash memory and other resources. The GW1NR series of FPGA products are the first generation of the Gowin ® LittleBee family and it is a SIP chip.

  • Page 11: A Development Board Suite

    2 Development Board Introduction 2.2 A Development Board Suite 2.2 A Development Board Suite A development board suite includes the following items: DK-START-GW1NR9 V2.1 Development Board  USB Cable  Figure 2-2 A Development Board Suite ① DK-START-GW1NR9 V2.1 Development Board ②...

  • Page 12: Pcb Components

    2 Development Board Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components LVDS 2.5V 1.2V 3.3V 1.8V FPGA Download 5V IN FPGA Switch GPIO GPIO LVDS LVDS 2.4 System Diagram Figure 2-4 System Diagram 2*BUTTON 2*SWITCH 4*LED 50MHz 5Pairs 10Pairs LVDS/MIPI...

  • Page 13: Feature

    2 Development Board Introduction 2.5 Feature 2.5 Feature The structure and feature of the development board are as follows: 1. FPGA LQFP144 package  Up to 120 user I/O  Embedded flash, data not easily lost if power down  Abundant LUT4 resources ...

  • Page 14: Development Board Specification

    2 Development Board Introduction 2.6 Development Board Specification 2.6 Development Board Specification Table 2-1 Development Board Specification Item Functional Description Technical Condition Note – – FPGA Core chip Support an USB USB to JTAG chip integrated on – Download interface; Support board JTAG, AUTOBOOT ...
  • Page 15 2 Development Board Introduction 2.6 Development Board Specification Item Functional Description Technical Condition Note – – Humidity Temperature – Operating range: –20° ~70° – DBUG384-1.3E 8(27)

  • Page 16: Development Board Circuit

    3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module 3.1.1 Overview The resources of GW1NR series of FPGA products are shown in Table 3-1. Table 3-1 GW1NR-9 FPGA Resources List Device GW1NR-9 LUT4 8,640 Flip-Flop (FF) 6,480 Shadow SRAM 17,280...

  • Page 17: I/O Bank Introduction

    3 Development Board Circuit 3.1 FPGA Module 3.1.2 I/O BANK Introduction There are four I/O Banks in the GW1NR series of FPGA products, as shown in Figure 3-1. Figure 3-1 GW1NR series FPGA Products I/O Bank Distribution Figure 3-2 GW1NR-9 LQ144 Package Pinout (Top View) DBUG384-1.3E 10(27)

  • Page 18: Download

    3 Development Board Circuit 3.2 Download Table 3-2 FPGA I/O Pinout I/O BANK No. Modules Connected  Pins for download mode I/O BANK0  MIPI/LVDS differential input  GPIO  GPIO  50MHz clock input I/O BANK1   Slide Switches ...

  • Page 19: Download Flow

    3 Development Board Circuit 3.3 Power Supply 3.2.3 Download Flow Please plug USB download cable into the USB interface (J6) of the development board to download FPGA, and then open Programmer, click SRAM mode or Embedded flash mode to download bit stream file to SRAM or flash.

  • Page 20: Power System Distribution

    3 Development Board Circuit 3.3 Power Supply 3.3.2 Power System Distribution Figure 3-4 Power System Distribution USB Interface DC5V Input USB to JTAG （FT2232） TPS7A7001 3.3V Key&LED&Reset& switch FPGA VCCO2 (LVDS) TPS7A7001 FPGA 2.5V VCCX&VCCO0 &VCCO1 TPS7A7001 FPGA VCCO3 (PSRAM) 1.8V FPGA VCCO2&VCCO0&...

  • Page 21: Pinout

    3 Development Board Circuit 3.4 Clock 3.3.3 Pinout Table 3-4 FPGA Power Pinout Signal Name Pin No. BANK Description I/O Level VCCO0 109, 127 I/O Bank Voltage 2.5V/1.2V VCCO1 91, 103 I/O Bank Voltage 2.5V/1.2V VCCO2 37, 55 I/O Bank Voltage 2.5V/1.2V VCCO3 9, 19...

  • Page 22: Led

    3 Development Board Circuit 3.5 LED 3.5 LED 3.5.1 Overview There are four green LEDs in the development board and users can display the required status through the LED. There are two LEDs left to facilitate the observation of power supply and FPGA loading status. Users can test the LEDs in the following ways: When the FPGA corresponding pin output signal is logic low , the LED ...

  • Page 23: Switches

    3 Development Board Circuit 3.6 Switches 3.6 Switches 3.6.1 Overview There are two slide switches in the development board to control input during testing. 3.6.2 Switch Circuit Figure 3-7 Switch Circuit 3.6.3 Pinout Table 3-7 Switch Circuit Pinout Signal Name Pin No.

  • Page 24: Key

    3 Development Board Circuit 3.7 Key 3.7 Key 3.7.1 Overview There are two key switches in the development board. Users can manually input low level to the corresponding FPGA pins for testing purposes. 3.7.2 Key Circuit Figure 3-8 Key Circuit 3.7.3 Pinout Table 3-8 Key Circuit Pinout Signal Name...

  • Page 25: Gpio

    3 Development Board Circuit 3.8 GPIO 3.8 GPIO 3.8.1 Overview One 2.54mm DC3-20P socket and one 2.54mm DC3-40P socket are reserved in the development board to facilitate the users to do the function expansion and testing. 3.8.2 GPIO Circuit Figure 3-9 GPIO Circuit H_B_IO1 H_B_IO2 H_B_IO4...

  • Page 26: Pinout

    3 Development Board Circuit 3.8 GPIO 3.8.3 Pinout Table 3-9 J14 GPIO Pinout Signal Name FPGA Socket BANK Description I/O Level Pin No. Pin No. H_A_IO1 General I/O 1.8V H_A_IO2 General I/O 1.8V H_A_IO3 General I/O 1.8V H_A_IO4 General I/O 1.8V H_A_IO5 General I/O...
  • Page 27 3 Development Board Circuit 3.8 GPIO FPGA Socket Signal Name BANK Description I/O Level Pin No. Pin No. H_B_IO10 General I/O 2.5V/1.2V H_B_IO11 General I/O 2.5V/1.2V H_B_IO12 General I/O 2.5V/1.2V H_B_IO13 General I/O 2.5V/1.2V H_B_IO14 General I/O 2.5V/1.2V H_B_IO15 General I/O 2.5V/1.2V H_B_IO16 General I/O...

  • Page 28: Mipi/Lvds

    3 Development Board Circuit 3.9 MIPI/LVDS 3.9 MIPI/LVDS 3.9.1 Overview Two 2 mm DC3-20P sockets are reserved in the development board for MIPI/LVDS input/output performance testing and high-speed data transmission. Up to 5 pairs of differential input and 9 pairs of differential output can be satisfied.

  • Page 29: Pinout

    3 Development Board Circuit 3.9 MIPI/LVDS 3.9.3 Pinout Table 3-11 J15 FPGA Pinout (IDES16:1 Supported) FPGA Socket Signal Name BANK Description I/O Level Pin No. Pin No. Differential input 2.5V/1.2V(LVD F_LVDS_A1_P channel 1+ S/MIPI) Differential input 2.5V/1.2V(LVD F_LVDS_A1_N channel 1- S/MIPI) Differential input 2.5V/1.2V(LVD...

  • Page 30: Table 3-12 J16 Fpga Pinout (Oser16:1 Supported)

    3 Development Board Circuit 3.9 MIPI/LVDS Table 3-12 J16 FPGA Pinout (OSER16:1 Supported) Signal Name FPGA Socket BANK Description I/O Level Pin No. Pin No. Differential output 2.5V(LVDS)/ F_LVDS_B1_P channel 1+ 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_B1_N channel 1- 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_B2_P channel 2+...

  • Page 31: Table 3-13 J18 Fpga Pinout (Oser16:1 Supported)

    3 Development Board Circuit 3.9 MIPI/LVDS Table 3-13 J18 FPGA Pinout (OSER16:1 Supported) FPGA Socket Signal Name BANK Description I/O Level Pin No. Pin No. Differential output 2.5V(LVDS)/ F_LVDS_B6_P channel 6+ 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_B6_N channel 6- 1.2V(MIPI)  Differential output 2.5V(LVDS)/ F_LVDS_B7_P...

  • Page 32: Considerations

    4 Considerations Considerations Considerations for the use of the development board: 1. Handle with care and pay attention to electrostatic protection; 2. VCCO2 Bank voltage needs to be set as 2.5V when the Bank2 output differential pairs serve as LVDS output; VCCO2 Bank voltage needs to be set as 1.2V when the Bank2 output differential pairs serve as MIPI output.

  • Page 33: Gowin Software

    5 Gowin Software Gowin Software Please refer to SUG100, Gowin Software User Guide for details. DBUG384-1.3E 26(27)

  • Page 34: Quick Start

    6 Quick Start Quick Start See TN436, DK-START-GW1NR9 Development Board Quick Start User Guide DBUG384-1.3E 27(27)

Table of Contents