Peg (Pci Express Graphics X16) Connector - Seco COM-Express CCOMe-965 User Manual

3.3.16 PEG (PCI Express Graphics x16) Connector

According to COM Express specifications, it is possible to expand the graphical capabilities of the board by using the
dedicated PCI Express Graphics x16 bus (PEG) interface, which can be accessed through a card edge connector type
TYCO p/n 2-1612163-4 or equivalent, with the pinout shown in the following table.
Please check the User Manual of the COM Express module used for details about the availability of these lanes.
Please be aware that PCI-e management on CCOMe-965 carrier board requires that the add-in card placed on this
slot manages the Hot Plug presence detect pins (B81/B48/B31/B17 and A1). More exactly, according to the PCI Express Card Electromechanical Specification
v3.0, it is required that these pins are tied together on the ADD-in Card (at least, it is needed that pin A1 is connected with one of the other pins, B17, B31, B48 or
B81).
In case that these pins are not tied together on the add-in card, then the carrier board will not acknowledge the presence of the card in the slot, and will not enable
the reference clock (and the add-in card will not work).
Description
+12V Power Rail
+12V Power Rail
+12V Power Rail
Power Ground
SM Bus Clock line
SM Bus Data line
Power Ground
+3.3V Power Rail
TRST#, tied to GND with 4K7Ω resistor
+3.3V Auxiliary Power Rail
Wake signal for link reactivation
Not Connected
Power Ground
PCI-e Graphics Transmitter lane 0+
PCI-e Graphics Transmitter lane 0-
Power Ground
CCOMe-965
CCOMe-965 - Rev. First Edition: 1.0 - Last Edition: 3.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
PCI Express Graphics x16 Slot- CN3
Pin name Pin nr. Pin nr.
+12V_S B1 A1
+12V_S B2 A2
+12V_S B3 A3
GND B4 A4
SMB_CK B5 A5
SMB_DAT B6 A6
GND B7 A7
+3.3V_S B8 A8
JTAG1 B9 A9
+3.3V_A B10 A10
WAKE0# B11 A11
RSVD B12 A12
GND B13 A13
PEG_TX0+ B14 A14
PEG_TX0- B15 A15
GND B16 A16
Pin name Description
GND Hot Plug presence detect (tied to GND)
+12V_S +12V Power Rail
+12V_S +12V Power Rail
GND Power Ground
JTAG2
TCK, tied to GND with 4K7Ω resistor
JTAG3
TDI, tied to +3.3V_S with 4K7Ω resistor
JTAG4 Test Data Out, not connected
JTAG5 TMS, tied to +3.3V_S with 4K7Ω resistor
+3.3V_S +3.3V Power Rail
+3.3V_S +3.3V Power Rail
PEG_RST# Reset signal to the add-in card
GND Power Ground
PCIE_CLK0+ PCI-e Graphics reference clock lane +
PCIE_CLK0- PCI-e Graphics reference clock lane -
GND Power Ground
PEG_RX0+ PCI-e Graphics Receiver lane 0+
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