Peg (Pci Express Graphics X16) Connector - Seco COM-Express CCOMe-C96 User Manual

PEG (PCI Express Graphics x16) Connector

According to COM Express specifications, it is possible to expand the graphical capabilities of the board by using the
dedicated PCI Express Graphics x16 bus (PEG) interface, which can be accessed through a card edge connector type
LOTES p/n APCI0470-P002C or equivalent, with the pinout shown in the following table.
Please check the User Manual of the COM Express module used for details about the availability of these lanes.
Please be aware that availability of these PCI express lanes depends on the COM Express module used.
Please check the User Manual of the COM Express module used for details about the availability of these lanes and all possible groupings that can be applied to
these lanes.
Description
+12V Power Rail
+12V Power Rail
+12V Power Rail
Power Ground
SM Bus Clock line. +3.3V_RUN electrical level with
up resistor, derived by SMB_CK with
mosfet voltage level converter
SM Bus Data line. +3.3V_RUN electrical level with
up resistor, derived by SMB_DAT with
mosfet voltage level converter
Power Ground
+3.3V Power Rail
TRST#, tied to GND with 4K7Ω resistor
+3.3V Auxiliary Power Rail
Wake signal for link reactivation
Not Connected
Power Ground
CCOMe-C96
CCOMe-C96 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R. - Reviewed by C.M. Copyright © 2021 SECO S.p.A.
PCI Express Graphics x16 Slot- CN13
Pin name Pin nr. Pin nr.
+12V_RUN B1 A1
+12V_RUN B2 A2
+12V_RUN B3 A3
GND B4 A4
PCIE_ SMB_CLK B5 A5
PCIE_ SMB_DAT B6 A6
GND B7 A7
+3.3V_RUN B8 A8
JTAG1 B9 A9
+3.3V_ALW B10 A10
WAKE0# B11 A11
RSVD B12 A12
GND B13 A13
Pin name Description
GND Hot Plug presence detect (tied to GND)
+12V_RUN +12V Power Rail
+12V_RUN +12V Power Rail
GND Power Ground
JTAG2 TCK, tied to GND with 4K7Ω resistor
JTAG3
TDI, tied to +3.3V_RUN with 4K7Ω resistor
JTAG4 Test Data Out, not connected
JTAG5 TMS, tied to +3.3V_RUN with 4K7Ω resistor
+3.3V_RUN +3.3V Power Rail
+3.3V_RUN +3.3V Power Rail
Reset signal to the add-in card, derived by
CB_RESET# using a Ultra High Speed CMOS
PEG_RST#
buffer. Active low signal, +3.3V_ALW electrical level
with a 100k
GND Power Ground
PCI-e reference clock lane +, derived by
PEG_CLK+
PCIE_CK_REF+ using a Clock Buffer
39