Yamaha O2R96 Service Manual page 68

02R96
TC7S04F (XM182A00)
AD1: IC003
ADA: IC003
DA: IC900
Inverter Gate
NC 1
IN 2
3
VSS
TC7SH32FU (TE85L) (XW633A00)
DSP: IC051
Input OR Gate
IN B
1
IN A 2
3
GND
CY2305 (XY937A00)
CPU1: IC114
Clock Buffer
Block Diagram
PLL
1
REF
S2
Select Input
Decoding
S1
68
TC7SH04FU (XS775A00)
CPU1: IC122
DSP: IC012, 066
Inverter Gate
5 VDD NC
IN A
4
OUT GND
TA7291F (XW618A00)
FD1: IC114-129
FD2: IC111-119
Motor Driver
Vcc
Vcc
5
4
OUT Y
IN1
8
CLKOUT
MUX
3
CLKA1
2
CLKA2
5
CLKA3
7
CLKA4
3
CLKB1
2
CLKB2
5
CLKB3
7
CLKB4
1 5 VCC
2
3 4
OUT Y
Vref
11 5
REG
Protector circuit
(Heat interception)
7 9 1
GND
IN2
1
8
REF CLK OUT
CLK2 2 7
CLK4
3
CLK1 6
VDD
4
GND 5
CLK3
TC7SH08FU (XR680A00)
CPU1: IC123, 137
2 Input AND Gate
IN B
1
IN A 2
3
GND
GND 1
15
Vs
NC 2
NC
3
OUT1
OUT1 4
4
M
Vref 5
13
OUT2
NC 6
IN1 7
NC 8
Pin No. Signal Function
1 REF Input reference frequency, 5V-tolerant input
2 CLK2 Buffered clock output
3 CLK1 Buffered clock output
4 GND Ground
5 CLK3 Buffered clock output
6 VDD 3.3V supply
7 CLK4 Buffered clock output
8 CLKOUT Buffered clock output, internal feedback on this pin
Vcc
5
4
OUT Y
16 NC
15
Vs
14 NC
13 OUT2
12
NC
11
Vcc
10 NC
IN2
9