Yamaha O2R96 Service Manual page 294

G
BLOCK DIAGRAM 004 (02R96)
LCDCOM (CNT)
(LCD Contrast)
LCD Unit
VR951
320 x 240 dot
(CFL BACK LIGHT)
CN951 (3P)
CN904 CN904
CN904 (14P) CN905 (4P) (14P) (14P) CN902 (3P)
IC901 (9P)
DC/DC DC/AC
CONVERTER INVERTER
(VEE:-24V) (BACK LIGHT)
CN903
(12P)
LCDCOM (INV)
CN901 (4P)
+12V
(from BRG)
38CA1-8823677-4
F E
CPU1
IC130 (32P)
SRAM
1Mbit
IC129 (60P)
LCD
Controller
CN106
SED1335F0B
(12P)
5V 3.3V
IC128 (24P)
Realtime
Clock
(RTC-62423)
D
(for DIAG)
IC108,109 (54P)
SmartMedia SDRAM
Interface 64Mbit X 2
for DEBU
DATA/ADDRESS-BUS
(D:32bit, A:26bit)
IC106,107
IC102-105 (32P) (48P)
SRAM Flash ROM
4Mbit X 4 16Mbit X 2
RESET
Battery backup
3.3V
IC138 (8P)
RESET
Reset/Backup
Controller
C
DSP SUB
(SEE Page 3) (SEE Page 6)
SUB CPU
MIDI I/F SCI1
BUS
CN104 (80P),
CN701 (6P)
CN105 (80P)
CN104 (80P),
CN101 (6P)
CN105 (80P)
IC101
(208P)
SCI2 SCI1
(UART) (UART)
SH-3 CPU
(SH7709A)
BUS
CPU: 96MHz
BUS: 32MHz
RESET
X101
8MHz
CPU Block
BLOCK DIAGRAM 004 (02R96)
B
02R96
1
SUB CPU
RESET
2
3
4
5
5