X
W
V
U
T
PN2 CIRCUIT DIAGRAM 002 (MB02R96)
1
2
3
not used
(for DSP check)
4
5
6
7
NOTE:
ON: BOOT MODE
8
9
10
11
12
13
14
15
16
38CC1-8823575-2
1
8
17
S
R
Q
P
O
BUFFER
NAND
Notation for Circuit Diagrams
N
M
L
K
J
DECODER
CPU
SYSTEM RESET
I
H
G
F
E
D
TRANSCEIVER
PN2 CIRCUIT DIAGRAM 002 (MB02R96)
C
B
A
MB02R96
to PN1-CN101
to PN1-CN100