3.11.1 Pin Description
Table 28: Electronic characteristic
Pin name
PCM_CLK
PCM_SYNC
PCM_DOUT
PCM_DIN
Table 29: Pin description
Pins
PCM_DIN/GPIO0
PCM_SYNC/GPIO2
PCM_DOUT/GPIO5
PCM_CLK/GPIO3
3.11.2 Signal Description
The default PCM interface in SIM5215&SIM5216 is the auxiliary PCM interface. The data changes on the
high level of PCM_CLK and is sampled at the falling edge of PCM_CLK in one period. Primary PCM is
disabled after every power-on or every reset event. So user must use AT command to enable the primary
PCM mode after powering on or resetting the module every time if user wants to use Primary
PCM.SIM5215&SIM5216 PCM Interface can be operated in Master or Slave mode if it is configured to
primary PCM. In Master Mode, the Module drives the clock and sync signals that are sent to the external
codec. When it is in Slave Mode, the external codec drives the clock and sync signals which are sent to the
module. Both PCM modes are discussed in this section followed by additional PCM topics.
Auxiliary PCM (128 KHz PCM clock)
υ -law coding is supported by the auxiliary PCM. The auxiliary codec port operates with standard
long-sync timing and a 128 KHz clock. The AUX_PCM_SYNC runs at 8 KHz with 50% duty cycle.
Most υ -law codec support the 128 KHz clock.
SIM5215&SIM5216_Hardware Design_V2.02
Min
2.5
2.5
2.5
2.5
AUX_PCM
Pin No.
functionality
74
AUX_PCM_DIN
75
AUX_PCM_SYNC
73
AUX_PCM_DOUT
76
AUX_PCM_CLK
Figure 34: Synchrony timing
Smart Machine Smart Decision
2.6V mode
Typ
2.6
2.6
2.6
2.6
Primary PCM
functionality
PCM_DIN
PCM_SYNC
PCM_DOUT
PCM_CLK
47
Max
2.7
2.7
2.7
2.7
Description
PCM data input
PCM data synchrony
PCM data output
PCM data clock
2012-08-31
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